Distributed arithmetic FPGA design with online scalable size and performance

ABSTRACT

The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design

Keywords:
FPGA, arithmetic, multitasking, reconfiguration