Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST

ABSTRACT

Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the whole SoC. This paper discusses the impact on the global system testing time of an analog BIST method based on digital reuse. Experimental results show that the reuse of digital blocks to test analog signals is indeed a very efficient strategy, even under power constraints, as long as the BIST technique reduces the analog testing time.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Design, Verification

Keywords:
BIST, mixed-signal test, power aware, system-on-chip