| ATPG for fault diagnosis on analog electrical networks using evolutionary techniques |
| Full text |
Pdf
(193 KB)
|
| Source
|
SBCCI
archive
Proceedings of the 17th symposium on Integrated circuits and system design
table of contents
Pernambuco, Brazil
SESSION: Test (co-organized with LA-TTTC)
table of contents
Pages: 100 - 104
Year of Publication: 2004
ISBN:1-58113-947-0
|
|
Authors
|
|
| Sponsor |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 1
|
|
|
ABSTRACT
This paper proposes a method for automated test pattern generation for fault diagnosis on continuous-time analog electrical networks based on evolutionary techniques. The paper states a method for coding a generic algorithm, based on a given heuristic, that are able to generate a set of optimum frequencies capable to disclose parametric faults. The method itself is generic, and not based on specific or ad hoc features at all.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
Rechenberg, I.: Evolutionsstrategie - Optimierung technischer Systeme nach Prinzipien der biologischen Evolution. Stuttgart: Frommann-Holzboog, 1973.
|
| |
3
|
Fogel, L. J., Owens, A. J. and Walsh, M. J.: Artificial Intelligence through Simulated Evolution. New York: John Wiley, 1966.
|
| |
4
|
|
| |
5
|
|
| |
6
|
Savioli, C.E.F, Szendrodi, C. E.,,Calvano, J.V.; Mesquita Filho, A.C.; Lubaszewski. A Rank-Based Genetic Algorithm for Fault Tolerant Analog Circ. Synth.,LATW'03.
|
| |
7
|
|
| |
8
|
Zebulum, Ricardo S. et al.-Evolutionary Electronics- Automatic Design of Circ.& Syst. by Genetic Algorithms. CRC Press, 20002.
|
| |
9
|
Lohn, Jason D. et al.-A Circuit Representation Technique for Automated Circuit Design-IEEE Trans. on Evolutionary Comp. Vol.3, No. 3, Sep 99.
|
| |
10
|
Savioli, C.E., C.C.Szendrodi, J.V. Calvano & M. S. Lubaszewski, The Use of Evolutionary Circuits for Designing for Robustness Analog Circuits, IMSTW'03.
|
| |
11
|
|
|