Characterization of MOS transistor current mismatch

ABSTRACT

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, and allows the assessment of mismatch from process and geometric parameters.

REFERENCES

• 1: J-B Shyu, G. C. Temes, and F. Krummenacher, "Random error effects in matched MOS capacitors and current sources", IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 948--955, Dec. 1984.
• 2: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors", IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433--1440, Oct. 1989.
• 3: F. Forti and M. E. Wright, "Measurements of MOS current mismatch in the weak inversion region", IEEE J. Solid-State Circuits, vol. 29, no. 2, pp. 138--142, Feb. 1994.
• 4: P. G. Drennan, and C. C. McAndrew, "Understanding MOSFET mismatch for analog design", IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 450--456, Mar. 2003.
• 5: M-F. Lan and R. Geiger, "Impact of model errors on predicting performance of matching-critical circuits, Proc. 43rd. IEEE Midwest Symp. on Circuits and Systems, pp.1324--1328, 2000.
• 6: H. Yang et al., " Current mismatch due to local dopant fluctuations in MOSFET channel", IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2248--2254, Nov. 2003.
• 7: C. Galup-Montoro, M. C. Schneider, A. Arnaud and H. Klimach, "Self-consistent models of DC, AC, noise and mismatch for the MOSFET", Proc. 2004 Nanotechnology Conference and Trade Show, pp. 494--499, 2004.
• 8: H. Klimach, A. Arnaud, M. C. Schneider and C. Galup-Montoro, "Consistent model for drain current mismatch in MOSFETs using the carrier number fluctuation theory", Proc. 2004 IEEE Int. Symposium on Circuits and Systems, 2004.
• 9: A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, "An MOS transistor model for analog circuit design", IEEE J. Solid-State Circuits, vol.33, no.10, pp.1510--1519, Oct.1998.
• 10: Current-Based MOSFET Model for Integrated Circuit Design", Chapter 2 in Low-Voltage/Low-Power Integrated Circuits and Systems, edited by E. Sánchez-Sinencio and A. Andreou, New Jersey: IEEE Press, 1998.
• 11: H. P. Tuinhout, "Design of matching test structures", Proc. IEEE 1994 Int. Conference on Microelectronic Test Structures, pp. 21--27, 1994.
• 12: M. Quarantelli et al., "Characterization and modeling of MOSFET mismatch of a deep submicron technology", Proc. IEEE 2003 Int. Conference on Microelectronic Test Structures, pp. 238--243, 2003.
• 13: T. Mizuno, "Influence of statistical spacial-nonunifirmity of dopant atoms on threshold voltage in a system of many MOSFETs", Jpn. J. Appl. Phys., vol. 35, pp. 842--848, 1996.
• 14: S. J. Lovett et al., "Sensitivity of MOS transistor mismatch to device dimensions and suggestions on how to improve matching performance", Proc. IEEE 1995 Colloquium on Improving the Efficiency of IC Manufacturing Technology, pp.11/1 -- 11/5, 1995.
• 15: M. Pelgrom and M. Vertregt, "CMOS technology for mixed signal ICs", Solid-State Electronics, vol. 41, no. 7, pp. 967--974, July 1997.
• 16: M. Steyaert et al., "Threshold voltage mismatch in short-channel MOS transistors", Electronics Letters , vol. 30 , no. 18 , pp. 1546 -- 1548, Sept. 1994.
• 17: R. Difrenza et al., "Impact of grain number fluctuations in the MOS transistor gate on matching performance", Proc. IEEE 2003 Int. Conference on Microelectronic Test Structures, pp. 244--249, 2003.
• 18: A. Arnaud and C. Galup-Montoro, "A compact model for flicker noise in MOS transistors for analog circuit design", IEEE Trans. Electron Devices, vol. 50, no. 8, pp. 1815--1818, Aug. 2003.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
MOSFET, analog design, compact models, matching, mismatch