Synthesizable HDL generation method for configurable VLIW processors

ABSTRACT

This paper proposes a synthesizable HDL code generation method using a processor specification description. The proposed approach can change the number of slots and pipeline stages, and dispatching rule to assign operations to resources. In addition, designers can specify each instruction behavior using the specification language. A control logic, a decode logic, and a data path of VLIW processor are generated from the processor specification. Designers can explore ASIP design space using the proposed approach effectively, because the amount of description and the modification cost are small. Using this approach, it took about eight hours to design 36 VLIW processors. Moreover, this approach provides a 82% reduction on the average compared to the description of the HDL code.

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