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Preserving synchronizing sequences of sequential circuits after retiming
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Novel techniques in logic synthesis table of contents
Pages: 579 - 584  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Maher N. Mneimneh  University of Michigan
Karem A. Sakallah  University of Michigan
John Moondanos  Intel Corporation
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining correct initialization of circuits after retiming optimizations. It has been previously shown that forward retiming moves across fanout stems can destroy a synchronizing sequence. We build on this observation and introduce the notion of "invalid states" that might arise due to forward moves. We show that the set of synchronizing sequences of a given circuit can be preserved by modifying transitions from those invalid states. We present an algorithm that implicitly computes the set of invalid states. Then, we describe a post-retiming synthesis step that incrementally resynthesizes some next-state functions to alter the behavior of invalid states to ensure correct post-retiming initialization. We report promising experimental results on the ISCAS 89 benchmarks and on a set of retimed circuits from an Intel Pentium-III class microprocessor.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Olivier Coudert, and Jean Christophe Madre, "Symbolic Computation of the Valid States of a Sequential Machine: Algorithms and Discussion," in Proceedings of the International Workshop on Formal Methods in VLSI Design, January 1991.
 
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A. El-Maleh, T. Marchok, J. Rajski, and W. Maly, "Behavior and Testability Preservation Under the Retiming Transformation," in IEEE Transactions on Computer-Aided Design, vol. 16, pp. 528--543, May 1997.
 
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C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.
 
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M. Mneimneh and K. Sakallah, "REVERSE: Efficient Sequential Verification for Retiming," International Workshop on Logic Synthesis, 2003.
 
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E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephen, R. Brayton, and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential Circuit Synthesis." University of California, Berkeley, Tech. Report, May 1994.
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F. Somenzi, "CUDD: CU Decision Diagram Package Release 2.3.1," Technical Report, University of Colorado at Boulder, 2001.
Collaborative Colleagues:
Maher N. Mneimneh: colleagues
Karem A. Sakallah: colleagues
John Moondanos: colleagues