The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

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The flexible processor an approach for single-chip hardware emulation by dynamic reconfiguration

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

SESSION: (Special session) presentation + poster disscussion: university design contest table of contents

Pages: 557 - 558

Year of Publication: 2004

ISBN:0-7803-8175-0

Authors

Takeshi Ohkawa	Tohoku University, Sendai, Japan
Toshiyuki Nozawa	Tohoku University, Sendai, Japan
Masanori Fujibayashi	Tohoku University, Sendai, Japan
Naoto Miyamoto	Tohoku University, Sendai, Japan
Karnan Leo	Tohoku University, Sendai, Japan
Soichiro Kita	Tohoku University Sendai, Japan
Koji Kotani	Tohoku University, Sendai, Japan
Tadahiro Ohmi	Tohoku University, Sendai, Japan

Sponsors

IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

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abstract references collaborative colleagues

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ABSTRACT

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for a single chip emulation system is developed. It demonstrates the sequential execution of several sub-circuits divided temporally from an original large circuit. In order to accelerate emulation speed, a logic element, reducing total configuration data by 30% compared to conventional Look-Up-Table, and Temporal Communication Module (TCM) to support save/restore of circuit state and data communication among divided sub-circuits, are implemented on the Flexible Processor.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Trimberger , D. Carberry , A. Johnson , J. Wong, A time-multiplexed FPGA, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.22, April 16-18, 1997
	2	S. Sakaidani, N. Miyamoto and T. Ohmi, "Flexible Processor Based on Full-Adder / D-Flip-Flop Merged Module (FDMM)," Jpn. J. Appl. Phys. 40, (2001) p.2581
	3	N. Miyamoto, K. Leo, K. Kotani and T. Ohmi, "A Fine-Grained Programmable Logic Module with Small Amount of Configuration Data for Dynamically Reconfigurable Field Programmable Gate Array (FPGA)," Proc. of SSDM 2002, pp. 248--249
	4	T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, K. Leo, S. Kita, K. Kotani and T. Ohmi, "The Flexible Processor - Dynamically Reconfigurable Logic Array for Personal-use Emulation System", Digest of Technical Papers, 2003 symposium on VLSI circuits, pp. 279--282

Collaborative Colleagues:

Takeshi Ohkawa: colleagues

Toshiyuki Nozawa: colleagues

Masanori Fujibayashi: colleagues

Naoto Miyamoto: colleagues

Karnan Leo: colleagues

Soichiro Kita: colleagues

Koji Kotani: colleagues

Tadahiro Ohmi: colleagues

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