| A small-area high-performance 512-point 2-dimensional FFT single-chip processor |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2004 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
SESSION: (Special session) presentation + poster disscussion: university design contest
table of contents
Pages: 537 - 538
Year of Publication: 2004
ISBN:0-7803-8175-0
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Authors
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Naoto Miyamoto
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University of Tohoku, Aramaki, Aoba, Sendai, Japan
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Leo Karnan
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University of Tohoku, Aramaki, Aoba, Sendai, Japan
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Kazuyuki Maruo
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Advantest Laboratories Ltd., Matsubara, Kamiayashi, Aoba, Sendai, Japan
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Koji Kotani
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University of Tohoku, Aramaki, Aoba, Sendai, Japan
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Tadahiro Ohmi
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University of Tohoku, Aramaki, Aoba, Sendai, Japan
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IEEE Press
Piscataway, NJ, USA
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Downloads (6 Weeks): 9, Downloads (12 Months): 26, Citation Count: 0
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 ABSTRACT
We have designed an FFT processor based on the 2-stage cached-memory architecture, which integrates 552,000 transistors within an area of 2.8 x 2.8 mm2 with CMOS 0.35μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 μsec and a 2-dimensional one is only 23.8 msec at 133MHz operation. We have measured this processor consumes 439.6mW at 3.3V, 100MHz operation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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