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Memory access driven storage assignment for variables in embedded system design
Full text Publisher SitePublisher Site PdfPdf (87 KB)
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Embedded software table of contents
Pages: 478 - 481  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Yoonseo Choi  Korea Advanced Institute of Science and Technology, Korea
Taewhan Kim  Korea Advanced Institute of Science and Technology, Korea
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 10,   Citation Count: 0
Additional Information:

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ABSTRACT

It has been reported and verified in many design experiences that a judicious utilization of the page/burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangment of data variables in memory directly leads to a maximum utilization of the page/burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this paper, to improve the quality of existing solutions, we propose a new storage assignement technique, called zone_alignment, for variables, which effectively exploits an efficient 0-1 ILP formulation and the temporal locality of variables' accesses in code.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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N. D. Dutt, "Memory Organization and Exploration for Embedded Systems-on-Silicon," Inter. Conf. on VLSI and CAD, 1997.
 
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IBM, "IBM Cu-11 Embedded DRAM Macro," http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/4CBB96F927E2D6D6D287256B98004E1D98/$file/Cu11_embedded_DRAM.10.pdf, 2002.
 
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Fujitsu, "CS70DL Embedded DRAM," http://www.fme.fujitsu.com/products/asic/pdf/CS70DLFS.pdf, 1999.
 
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A. Khare et al., "High-Level Synthesis with Synchronous and RAMBUS DRAMs," SASIMI, 1998.
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K. Ayukawa et al., "An Access Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAMs," IEEE JSSC, 1998.
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Collaborative Colleagues:
Yoonseo Choi: colleagues
Taewhan Kim: colleagues