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ABSTRACT
This paper investigates a 3D die-stacking based VLSI integration strategy, so-called 2.5D integration, which can potentially overcome many problems stumbling the development of monolithic System-on-Chip (SoC). In this paper, we review available fabrication technologies and testing solutions for the new integration strategy. We also propose a design driven system implementation schema for this new integration strategy. A layout synthesis framework is under development by us to analyze typical "what if" questions and resolve major physical attributes for a 2.5D system according to the design specification and constraints.
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CITED BY 5
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Feihui Li , Chrysostomos Nicopoulos , Thomas Richardson , Yuan Xie , Vijaykrishnan Narayanan , Mahmut Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, ACM SIGARCH Computer Architecture News, v.34 n.2, p.130-141, May 2006
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Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb, Die Stacking (3D) Microarchitecture, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.469-479, December 09-13, 2006
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