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Model checking on state transition diagram
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: Formal verification table of contents
Pages: 412 - 417  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Batsayan Das  Comp Sc and Engg., IIT Kharagpur, India
Dipankar Sarkar  Comp Sc and Engg., IIT Kharagpur, India
Santanu Chattopadhyay  Comp Sc and Engg., IIT Guwahati, India
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
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ABSTRACT

Computation Tree Logic (CTL) model checking is sensitive to state explosion. Conventionally, CTL semantics is defined over Kripke structure where each state is labelled with all the atomic propositions. For open systems, this necessitates input labeling of the states. In contrast, the common model, which is used for sequential circuit design, is the finite state machine (FSM) model, or equivalently, the state transition diagram (STD), where the inputs are associated not with the states but with the transitions. Thus, to use a conventional CTL model checker, the STD has to be converted first to the Kripke structure and then applying the model checking algorithm on the Kripke structure. The need for associating input labels to the states results in state explosion which finally tells upon the model checking efficiency. The paper presents the CTL semantics over STD structures and develops a model checking algorithm which works directly over the STD. A performance gain over conventional model checking by an exponential factor results in the process, especially for open systems.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E. Clarke, O. Grumberg, and D. Peled, Model Checking. MIT Press, 2000.
 
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Z. Kohavi, Switching and Automata Theory. Tata-McGraw Hill, Pub. Co. Ltd., New Delhi, 1978.
 
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J. Burch, E. Clarke, K. McMillian, D. Dill, and L. Hawang, "Symbolic Model Checking for Sequential Circuit Verification," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol. 13(4), pp. 401--424, 1994.

Collaborative Colleagues:
Batsayan Das: colleagues
Dipankar Sarkar: colleagues
Santanu Chattopadhyay: colleagues