Mixed-clock issue queue design for energy aware, high-performance cores

ABSTRACT

Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal costs, as well as an enabler for allowing fine grain speed and voltage management. Due to its inherent complexity, a possible driver application for such a design style is the case of superscalar, out-of-order processors. This paper proposes a novel mixed-clock issue queue design, and compares and contrasts this new implementation with existing synchronous or mixed-clock versions of issue queues, used in stand-alone mode or in conjunction with mixed-clock FIFO (First-In, First-Out) buffers for inter-domain synchronization. Both transistor level, SPICE simulation, as well as cycle-accurate, microarchitectural analysis, show that cores using mixed-clock issue queues are able to provide better energy-performance operating points when compared to their synchronous or asynchronous FIFO-based counterparts.

REFERENCES

• 1: Kerry Bernstein , Keith M. Carrig , Christopher M. Durham , Patrick R. Hansen , David Hogenmiller , Edward J. Nowak , Norman J. Rohrer, High speed CMOS design styles, Kluwer Academic Publishers, Norwell, MA, 1998
• 2: Robert W. Brodersen , Mark A. Horowitz , Dejan Markovic , Borivoje Nikolic , Vladimir Stojanovic, Methods for true power minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.35-42, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774578]
• 3: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 4: D. Burger, T. Austin, "The Simple Scalar Toolset," University of Wisconsin, CSD Technical Report #1342, June 1997.
• 5: Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
• 6: Daniel Marcos Chapiro, Globally-asynchronous locally-synchronous systems (performance, reliability, digital), 1985
• 7: Tiberiu Chelcea , Steven M. Nowick, Robust interfaces for mixed-timing systems with application to latency-insensitive protocols, Proceedings of the 38th conference on Design automation, p.21-26, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378256]
• 8: William J. Dally , John W. Poulton, Digital systems engineering, Cambridge University Press, New York, NY, 1998
• 9: L. Ding and P. Mazumder, "On Optimal Tapering of FET Chains in High-Speed CMOS Circuits," in IEEE Transactions on Circuits and Systems II, vol. 48, pp. 1099--1109, Dec 2001.
• 10: J. A. Farell and T. C. Fischer, "Issue Logic for a 600-MHz Out-of-Order Execution Microprocessor," in IEEE Journal of Solid-State Circuits, vol. 33, pp. 707--712, May 1998.
• 11: Anoop Iyer , Diana Marculescu, Power efficiency of voltage scaling in multiple clock, multiple voltage cores, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.379-386, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774629]
• 12: David E. Lackey , Paul S. Zuchowski , Thomas R. Bednar , Douglas W. Stout , Scott W. Gould , John M. Cohn, Managing power and performance for System-on-Chip designs using Voltage Islands, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.195-202, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774601]
• 13: J. Leenstra, J. Pille, A. Mueler, W. M. Sauer, D. F. Wendel, "A 1.8 GHz Instruction Window Buffer for an Out-of-Order Microprocessor Core," in IEEE Journal of Solid-State Circuits, vol. 36, pp. 1628--1635, Nov. 2001.
• 14: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 15: Greg Semeraro , David H. Albonesi , Steven G. Dropsho , Grigorios Magklis , Sandhya Dwarkadas , Michael L. Scott, Dynamic frequency and voltage control for a multiple clock domain microarchitecture, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 16: Allen E. Sjogren , Chris J. Myers, Interfacing synchronous and asynchronous modules within a high-speed pipeline, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.8 n.5, p.573-583, Oct., 2000 [doi>10.1109/92.894162]
• 17: Ivan Sutherland , Bob Sproull , David Harris, Logical effort: designing fast CMOS circuits, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1999
• 18: Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460]
• 19: Venkata Syam P. Rapaka , Diana Marculescu, A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871600]
• 20: V. S. P. Rapaka, "Design and Analysis of Mixed-Clock Issue Queues for Globally Asynchronous, Locally Synchronous Processor Cores," Master's Thesis, Technical Report CSSI 03-05, Carnegie Mellon University, June 2003.