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NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Full text Publisher SitePublisher Site PdfPdf (232 KB)
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2004 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
SESSION: RF design methodology table of contents
Pages: 169 - 174  
Year of Publication: 2004
ISBN:0-7803-8175-0
Authors
Min Chu  University of Washington, Seattle, WA
David J. Allstot  University of Washington, Seattle, WA
Jeffrey M. Huard  National Semiconductor Corporation, Federal Way, WA
Kim Y. Wong  National Semiconductor Corporation, Federal Way, WA
Sponsors
IEICE : Institute of Electronics, Information and Communication Engineers
: IEEE Circuits and Systems Society
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 26,   Citation Count: 4
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ABSTRACT

A parasitic-aware RF synthesis tool based on a non-dominated sorting genetic algorithm (NSGA) is introduced. The NSGA-based optimizer casts the design problem as a mulit-objective optimization problem and offers multiple solutions along the Pareto optimal front. Monte-Carlo simulations are then performed to efficiently assess sensitivity at solution points with respect to process, voltage, and temperature (PVT) variations. An example design of a 10mW 5GHz voltage-controlled oscillator (VCO) in 250nm SiGe BiCMOS achieves a 12% tuning range with a phase noise of - 133dBc/Hz at 3MHz offset. The Figure-of-Merit (FOM) is 188dBc/Hz and power-frequency-tuning normalized FOM (PFTN-FOM) is -4dB.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Min Chu: colleagues
David J. Allstot: colleagues
Jeffrey M. Huard: colleagues
Kim Y. Wong: colleagues