Efficient adaptive voltage scaling system through on-chip critical path emulation

ABSTRACT

Conventional voltage scaling techniques rely on the characterization and monitoring of a unique critical path. However, the uniqueness of the critical path is a difficult requirement to establish in modern VLSI technologies due to the growing impact of process variations and interconnect parasitics on delay. This paper presents an on-chip critical path emulator architecture which tracks the changing critical path. The ability to emulate the actual critical path recovers most of the large margin added by conventional systems to guarantee a robust operation at all conditions. Due to the reduced margin, the proposed architecture is up to 45% and 21% more energy efficient compared to conventional open-loop and closed-loop voltage scaling systems respectively.

REFERENCES

• 1: T. Burdphet.al, "A Dynamic Voltage Scaled Microprocessor System," JSSC, vol. 35, no. 11, pp. 1571--1580, Nov. 2000.
• 2: J. Kim and M. Horowitz, "An Efficient Digital Sliding Controller for Adaptive Power-Supply Regulation," JSSC, vol. 37, no. 5, pp. 639--647, May 2002.
• 3: Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
• 4: Semiconductor Industry Association, "Itrs, 2003 ed. http://www.public.itrs.net".
• 5: A. Chandrakasan , V. Gutnik , T. Xanthopoulos, Data driven signal processing: an approach for energy efficient computing, Proceedings of the 1996 international symposium on Low power electronics and design, p.347-352, August 12-14, 1996, Monterey, California, United States
• 6: G. Weiphet.al, "A Variable-Frequency Parallel I/O Interface with Adaptive Power-Supply Regulation," JSSC, vol. 35, no. 11, pp. 1600--1610, Nov. 2000.
• 7: R. Gonzalez and M. Horowitz, "Supply and Threshold Voltage Scaling for Low Power CMOS," JSSC, vol. 32, no. 9, pp. 1210--1216, Aug. 1997.
• 8: M. Elgebalyphet.al, "Robust and Efficient Dynamic Voltage Scaling Architecture," in ASIC/SOC, 2003, pp. 155--158.
• 9: T. Sakurai and R. Newton, "Delay Analysis of Series-Connected MOSFET Circuits," JSSC, vol. 26, no. 2, pp. 122--131, Feb. 1991.
• 10: J. Daga and D. Auvergne, "A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics," JSSC, vol. 34, no. 1, pp. 42--55, Jan. 1999.
• 11: R. Hophet.al, "The Future of Wires," IEEE Proc., vol. 89, no. 4, pp. 490--504, Apr. 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Performance

Keywords:
CMOS, adaptive voltage scaling, low-power