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Reducing pipeline energy demands with local DVS and dynamic retiming
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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2004 international symposium on Low power electronics and design table of contents
Newport Beach, California, USA
SESSION: Power efficient design for arithmetic circuits table of contents
Pages: 319 - 324  
Year of Publication: 2004
ISBN:1-58113-929-2
Authors
Seokwoo Lee  The University of Michigan, Ann Arbor, MI
Shidhartha Das  The University of Michigan, Ann Arbor, MI
Toan Pham  The University of Michigan, Ann Arbor, MI
Todd Austin  The University of Michigan, Ann Arbor, MI
David Blaauw  The University of Michigan, Ann Arbor, MI
Trevor Mudge  The University of Michigan, Ann Arbor, MI
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 19,   Citation Count: 7
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ABSTRACT

The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniques such as Razor DVS, voltage overscaling, and Intelligent Energy Management have emerged as approaches to further reduce voltage by eliminating costly voltage margins inserted into traditional designs to ensure always-correct operation. The degree to which a global voltage controller can shave voltage margins is limited by imbalances in pipeline stage latency. Since all pipeline stages share the same voltage, the stage exercising the longest critical path will define the overall voltage of the system, even if other stages could potentially run at lower voltages. In this paper, we evaluate two local tuning mechanisms in the context of Razor DVS, a local voltage controller scheme that allows each pipeline stages it's own voltage level, and a lower cost dynamic retiming scheme that incorporates per-stage clock delay elements to allow longer-latency pipeline stages to "borrow" time from shorter-latency stages.

Using simulation, we draw two key insights from our study. First, mitigating pipeline stage imbalances renders additional DVS energy savings. A Razor pipeline design with dynamic retiming finds an additional 12% energy savings over global voltage control (resulting in an overall energy savings of more than 28% compared to fully-margined DVS). Second, we demonstrate that imbalances arise not only from design factors, but also from run-time characteristics. As the program (or program phase) changes, we see different logic paths in multiple stages exercised frequently, necessitating a dynamic fine-tuning of local control. This result suggests that even well-balanced pipelines could benefit from dynamic retiming.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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T. Njølstad. et.al "A Socket Interface For GALS Using Locally Dynamic Voltage Scaling For Rate-Adaptive Energy Saving", IEEE 2001.
 
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R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and Threshold Voltage Scaling for Low Power CMOS", IEEE JSSC, 32 (8), August 1997.

CITED BY  7

Collaborative Colleagues:
Seokwoo Lee: colleagues
Shidhartha Das: colleagues
Toan Pham: colleagues
Todd Austin: colleagues
David Blaauw: colleagues
Trevor Mudge: colleagues