| Reducing pipeline energy demands with local DVS and dynamic retiming |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2004 international symposium on Low power electronics and design
table of contents
Newport Beach, California, USA
SESSION: Power efficient design for arithmetic circuits
table of contents
Pages: 319 - 324
Year of Publication: 2004
ISBN:1-58113-929-2
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Authors
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Seokwoo Lee
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The University of Michigan, Ann Arbor, MI
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Shidhartha Das
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The University of Michigan, Ann Arbor, MI
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Toan Pham
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The University of Michigan, Ann Arbor, MI
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Todd Austin
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The University of Michigan, Ann Arbor, MI
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David Blaauw
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The University of Michigan, Ann Arbor, MI
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Trevor Mudge
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The University of Michigan, Ann Arbor, MI
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 19, Citation Count: 7
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ABSTRACT
The quadratic relationship between voltage and energy has made
dynamic voltage scaling (DVS) one of the most powerful techniques
to reduce system power demands. Recently, techniques such as Razor
DVS, voltage overscaling, and Intelligent Energy Management have
emerged as approaches to further reduce voltage by eliminating
costly voltage margins inserted into traditional designs to ensure
always-correct operation. The degree to which a global voltage
controller can shave voltage margins is limited by imbalances in
pipeline stage latency. Since all pipeline stages share the same
voltage, the stage exercising the longest critical path will define
the overall voltage of the system, even if other stages could
potentially run at lower voltages. In this paper, we evaluate two
local tuning mechanisms in the context of Razor DVS, a local
voltage controller scheme that allows each pipeline stages it's own
voltage level, and a lower cost dynamic retiming scheme that
incorporates per-stage clock delay elements to allow longer-latency
pipeline stages to "borrow" time from shorter-latency stages.
Using simulation, we draw two key insights from our study.
First, mitigating pipeline stage imbalances renders additional DVS
energy savings. A Razor pipeline design with dynamic retiming finds
an additional 12% energy savings over global voltage control
(resulting in an overall energy savings of more than 28% compared
to fully-margined DVS). Second, we demonstrate that imbalances
arise not only from design factors, but also from run-time
characteristics. As the program (or program phase) changes, we see
different logic paths in multiple stages exercised frequently,
necessitating a dynamic fine-tuning of local control. This result
suggests that even well-balanced pipelines could benefit from
dynamic retiming.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
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Seokwoo Lee , Shidhartha Das , Valeria Bertacco , Todd Austin , David Blaauw , Trevor Mudge, Circuit-aware architectural simulation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
[doi> 10.1145/996566.996656]
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CITED BY 7
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Dan Ernst , Shidhartha Das , Seokwoo Lee , David Blaauw , Todd Austin , Trevor Mudge , Nam Sung Kim , Krisztian Flautner, Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation, IEEE Micro, v.24 n.6, p.10-20, November 2004
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Takeshi Kitahara , Hiroyuki Hara , Shinichiro Shiratake , Yoshiki Tsukiboshi , Tomoyuki Yoda , Tetsuaki Utsumi , Fumihiro Minami, Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
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Bonesi Stefano , Davide Bertozzi , Luca Benini , Enrico Macii, Process variation tolerant pipeline design through a placement-aware multiple voltage island design style, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
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D. Andrade , F. Martorell , A. Calomarde , F. Moll , A. Rubio, A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs, Microelectronics Journal, v.40 n.6, p.952-957, June, 2009
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