Power-optimal pipelining in deep submicron technology

ABSTRACT

This paper explores the effectiveness of pipelining as a power saving tool, where the reduction in logic depth per stage is used to reduce supply voltage at a fixed clock frequency. We examine power-optimal pipelining in deep submicron technology, both analytically and by simulation. Simulation uses a 70nm predictive process with a fanout-of-four inverter chain model including input/output flip-flops, and results are shown to match theory well. The simulation results show that power-optimal logic depth is 6 to 8 FO4 and optimal power saving varies from 55 to 80% compared to a 24 FO4 logic depth, depending on threshold voltage, activity factor, and presence of clock-gating.We decompose the power consumption of a circuit into three components, switching power, leakage power, and idle power, and present the following insights into power-optimal pipelining. First, power-optimal logic depth decreases and optimal power savings increase for larger activity factors, where switching power dominates over leakage and idle power. Second, pipelining is more effective with lower threshold voltages at high activity factors, but higher threshold voltages give better results at lower activity factors where leakage current dominates. Lastly, clock-gating enables deeper pipelining and more power saving because it reduces timing element overhead when the activity factor is low.

REFERENCES

• 1: Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
• 2: A. Chandrakasan et al. Low-power CMOS digital design. IEEE JSSC, 27(4):473--484, Apr. 1992.
• 3: Vivek De , Shekhar Borkar, Technology and design challenges for low power and high performance, Proceedings of the 1999 international symposium on Low power electronics and design, p.163-168, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313908]
• 4: Device Group at UC Berkeley. Predictive technology model. Technical report, UC Berkeley, 2001. http://www-device.eecs.berkely.edu/ptm/.
• 5: A. Hartstein , Thomas R. Puzak, The optimum pipeline depth for a microprocessor, Proceedings of the 29th annual international symposium on Computer architecture, p.7, May 25-29, 2002, Anchorage, Alaska
• 6: A. Hartstein , Thomas R. Puzak, Optimum Power/Performance Pipeline Depth, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.117, December 03-05, 2003
• 7: Seongmoo Heo , Ronny Krashinsky , Krste Asanovic, Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy, Proceedings of the 2001 Conference on Advanced Research in VLSI, p.59, March 14-16, 2001
• 8: G. Hinton et al. A 0.18µm CMOS IA-32 processor with a 4-GHz integer execution unit. IEEE JSSC, 36(11):1617--1627, Nov. 2001.
• 9: M. S. Hrishikesh , Doug Burger , Norman P. Jouppi , Stephen W. Keckler , Keith I. Farkas , Premkishore Shivakumar, The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
• 10: S. R. Kunkel , J. E. Smith, Optimal pipelining in supercomputers, Proceedings of the 13th annual international symposium on Computer architecture, p.404-411, June 02-05, 1986, Tokyo, Japan
• 11: Eric Sprangle , Doug Carmean, Increasing processor performance by implementing deeper pipelines, Proceedings of the 29th annual international symposium on Computer architecture, p.25, May 25-29, 2002, Anchorage, Alaska
• 12: Viji Srinivasan , David Brooks , Michael Gschwind , Pradip Bose , Victor Zyuban , Philip N. Strenski , Philip G. Emma, Optimizing pipelines for power and performance, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers; VLSI (very large scale integration)

General Terms:
Design, Performance, Theory

Keywords:
pipelining, power scaling, supply voltage reduction