Approaches to run-time and standby mode leakage reduction in global buses

ABSTRACT

In this paper, we present various design approaches to leakage minimization in global repeaters. We demonstrate the applicability of the MTCMOS scheme to global repeaters for leakage reduction. We then analyze two design approaches called Duplicated Skewed Buses and Skewed Pulsed Buses. We show that significant reduction in standby leakage power can be obtained using these approaches while providing significant improvements in performance. We also illustrate the use of these proposed techniques with the MTCMOS approach to obtain further savings in leakage power. Simulations results in a 90nm process show that skewed pulsed buses with MTCMOS can provide 20% improvement in performance with over 25% reduction in active mode leakage and nearly 100X reduction in standby mode leakage.

REFERENCES

• 1: International Technology Roadmap for Semiconductors, http://public.itrs.net/Files/2001ITRS/Home.htm, 2001.
• 2: Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron II: a global wiring paradigm, Proceedings of the 1999 international symposium on Physical design, p.193-200, April 12-14, 1999, Monterey, California, United States [doi>10.1145/299996.300073]
• 3: J. Cong, "Challenges and oppurtunities for design innovations in nanometer technologies," SRC working papers, http://www.src.org/prg_mgmt/frontier.dgw, 1997.
• 4: V. Adler and E. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. On Circuits and Systems II, vol. 45, pp. 607--618, 1998.
• 5: Kerry Bernstein , Ching-Te Chuang , Rajiv Joshi , Ruchir Puri, Design and CAD Challenges in sub-90nm CMOS Technologies, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.129, November 09-13, 2003 [doi>10.1109/ICCAD.2003.54]
• 6: Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640014]
• 7: DSM repeater insertion: satisfying delay constraints while minimizing area and power," 14th IEEE Intl. ASIC/SOC Conf., pp. 152--156, 2001.
• 8: Transition Aware Global Signaling (TAGS), Proceedings of the 3rd International Symposium on Quality Electronic Design, p.53, March 18-21, 2002
• 9: K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnections in nanometer designs," IEEE Trans. On Electron Devices, vol. 49, no. 11, pp. 2001--2007, 2002.
• 10: S. Mutoh, et.al, "A 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS," IEEE JSSC, vol. 30, no. 8, pp. 847--845, 1995.
• 11: Y. Ye, S. Borkar and V. De, "A new techniques for standby leakage reduction in high-performance circuits," Symp. on VLSI Circuits, pp. 40--41, 1998.
• 12: David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
• 13: Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar, Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871538]
• 14: J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," CICC, pp. 475--478, 1997.
• 15: Mark C. Johnson , Dinesh Somasekhar , Kaushik Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, Proceedings of the 36th ACM/IEEE conference on Design automation, p.442-445, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309976]
• 16: T. Kuroda, et.al, "A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Tranform Core Processor with variable threshold-voltage (VT) scheme," IEEE JSSC, vol.31, no. 11, pp. 1770--1779, 1996.
• 17: Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]
• 18: High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.227, September 17-20, 2000
• 19: F. Assaderaghi, et.al, "Dynamic threshold-voltage MOS (DTMOS) for ultra-low voltage VLSI," IEEE Trans. on Electron Devices, vol. 44, no. 3, pp. 414--422, 1997.
• 20: Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang , Peter W. Cook , Richard B. Brown, New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871548]
• 21: R. Rao, et.al, "Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies," ESSCIRC, pp. 313--316, 2003.
• 22: M. Khellal, et.al, "Static pulsed buses for on-chip interconnects," Symp. on VLSI Circuits, pp. 78--79, 2002.
• 23: L. Cotten, AFIPS Proc. Spring Joint Comp. Conf, vol. 34, pp. 581--586, 1969.
• 24: M. Khare, et.al, IEEE IEDM, pp. 407--410, 2002.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Performance

Keywords:
MTCMOS, leakage, pulsed buses, repeaters