Active mode leakage reduction using fine-grained forward body biasing strategy

ABSTRACT

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent problem which is leakage power reduction in active mode of operation. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose a fine-grained Forward Body Biasing (FBB) Scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal polynomial time FBB allocation scheme results in 70.2% reduction in leakage currents. We also present a novel placement-driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 39.7%, 64.7% and 67.1% reduction in leakage currents for 0%, 4% and 8% area slack respectively.

REFERENCES

• 1: Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337549]
• 2: A. J. Bhavnagarwala et al. "Dynamic-Threshold CMOS SRAM Cells for Fast, Portable Applications". In ASIC/SOC Conference, pages 359--363, 2000.
• 3: Adel S. Sedra , Kenneth C. Smith, Microelectronic circuits, 2nd ed., Holt, Rinehart & Winston, Austin, TX, 1987
• 4: Ali Keshavarzi et al. "Forward body Bias for Microprocessors in 130nm Technology Generation and Beyond". In VLSI Circuits Symp., pages 312--315, 2002.
• 5: Chris H. Kim , Kaushik Roy, Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566473]
• 6: Chris H. Kim , Jae-Joon Kim , Saibal Mukhopadhyay , Kaushik Roy, A forward body-biased low-leakage SRAM cache: device and architecture considerations, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871511]
• 7: D. S. Hochbaum , J. George Shanthikumar, Convex separable optimization is not much harder than linear optimization, Journal of the ACM (JACM), v.37 n.4, p.843-862, Oct. 1990 [doi>10.1145/96559.96597]
• 8: E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A.L. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Department of EECS. UC Berkeley, May 1992.
• 9: H. Kawaguchi et al. "Dynamic Leakage Cut-Off Scheme for Low-Voltage SRAM's". In VLSI Circuits Symp., pages 140--141, 1998.
• 10: R. Gu and M. Elmasry. "Power Dissipation Analysis and Optimization of Deep Submicron CMOS Digital Circuits". In IEEE JSSC, May 1996.
• 11: Saibal Mukhopadhyay , Kaushik Roy, Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871549]
• 12: S. Narendra et al. "1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS". In ISSCC, 2002.
• 13: T. Sakurai and A.R. Newton. "A Simple MOSFET Model for Circuit Analysis". In IEEE Transactions on Electron Devices, April 1991.
• 14: Y. Taur et al. "25 nm CMOS Design Considerations". In IEDM, pages 789--792, 1998.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design

Keywords:
forward body biasing, leakage power optimization