Post-layout leakage power minimization based on distributed sleep transistor insertion

ABSTRACT

This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysis on several benchmarks placed and routed with state-of-the art commercial tools for physical design.

REFERENCES

• 1: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 2: Low-power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels, Proceedings of the 3rd International Symposium on Quality Electronic Design, p.445, March 18-21, 2002
• 3: Dongwoo Lee , Wesley Kwong , David Blaauw , Dennis Sylvester, Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design, Proceedings of the 4th International Symposium on Quality Electronic Design, p.287, March 24-26, 2003
• 4: T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, T. Sakuray, "A 0.9-V, 150-MHz 10-mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1770-1779, November 1996.
• 5: H. Kawaguchi, K. Nose, T. Sakurai, "A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current," IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, pp. 1498--1501, October 2000.
• 6: Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]
• 7: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 8: Changbo Long , Lei He, Distributed sleep transistor network for power reduction, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775879]
• 9: Cadence Design Systems, BuildGates Extreme, www.cadence.com
• 10: Pietro Babighian , Luca Benini , Enrico Macii, Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating, Proceedings of the conference on Design, automation and test in Europe, p.10720, February 16-20, 2004

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Algorithms, Experimentation

Keywords:
leakage power, sleep transistor, sub-threshold current