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Understanding the energy efficiency of simultaneous multithreading
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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2004 international symposium on Low power electronics and design table of contents
Newport Beach, California, USA
SESSION: Microarchitecural techniques for power reduction table of contents
Pages: 44 - 49  
Year of Publication: 2004
ISBN:1-58113-929-2
Authors
Yingmin Li  University of Virginia
David Brooks  Harvard University
Zhigang Hu  IBM T.J. Watson Research Center
Kevin Skadron  University of Virginia
Pradip Bose  IBM T.J. Watson Research Center
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 24,   Citation Count: 7
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ABSTRACT

Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of critical importance, and we present modeling extensions to an architectural simulator to allow us to study the power-performance efficiency of SMT. After a thorough design space exploration we find that SMT can provide a performance speedup of nearly 20% for a wide range of applications with a power overhead of roughly 24%. Thus, SMT can provide a substantial benefit for energy-efficiency metrics such as ED2. We also explore the underlying reasons for the power uplift, analyze the impact of leakage-sensitive process technologies, and discuss our model validation strategy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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R. Kalla, B. Sinharoy, and J. Tendler. POWER5: IBM's next generation power microprocessor. In Proc. 15th Hot Chips Symp, pages 292--303, August 2003.
 
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D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture. Intel Technology Journal, 6(1):4--15, Feb. 2002.
 
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M. Moudgill, P. Bose, and J. H. Moreno. Validation of Turandot, a fast processor model for microarchitecture exploration. In Proceedings of IEEE Internatioanl Performance, Computing and Communications Conference, pages 451--457, February 1999.
 
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Y. Sazeides and T. Juan. How to compare the performance of two SMT microarchitectures. In IEEE International Symposium on Performance Analysis of Systems and Software, November 2001.
 
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REVIEW

"Hongzhang Shan : Reviewer"

Power consumption has become a major concern in microprocessor design. This paper presents a detailed study of the relative power-performance efficiency of simultaneous multithreading (SMT), a new microarchitectural paradigm, using a power-perform  more...

Collaborative Colleagues:
Yingmin Li: colleagues
David Brooks: colleagues
Zhigang Hu: colleagues
Kevin Skadron: colleagues
Pradip Bose: colleagues