Microarchitectural techniques for power gating of execution units

ABSTRACT

Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.

REFERENCES

• 1: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 2: Lawrence T. Clark , Neil Deutscher , Shay Demmons , Franco Ricci, Standby power management for a 0.18μm microprocessor, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566413]
• 3: Steven Dropsho , Volkan Kursun , David H. Albonesi , Sandhya Dwarkadas , Eby G. Friedman, Managing static leakage energy in microprocessor functional units, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
• 4: David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
• 5: Krisztián Flautner , Nam Sung Kim , Steve Martin , David Blaauw , Trevor Mudge, Drowsy caches: simple techniques for reducing leakage power, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
• 6: Fatih Hamzaoglu , Mircea R. Stan, Circuit-level techniques to control gate leakage for sub-100nm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566425]
• 7: Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
• 8: Vijay S. Iyengar , Louise H. Trevillyan , Pradip Bose, Representative Traces for Processor Models with Infinite Cache, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.62, February 03-07, 1996
• 9: Mark C. Johnson , Dinesh Somasekhar , Lih-Yih Chiou , Kaushik Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.1-5, 2/1/2002 [doi>10.1109/92.988724]
• 10: Kao, J., and Chandrakasan, A. Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journal of Solid State Circuits 35 (2000).
• 11: Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, Proceedings of the 28th annual international symposium on Computer architecture, p.240-251, June 30-July 04, 2001, Göteborg, Sweden
• 12: Moudgill, M., Bose, P., and Moreno, J. H. Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration. In IPCCC (1999).
• 13: Mayan Moudgill , John-David Wellman , Jaime H. Moreno, Environment for PowerPC Microarchitecture Exploration, IEEE Micro, v.19 n.3, p.15-25, May 1999 [doi>10.1109/40.768496]
• 14: Michael Powell , Se-Hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar, Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, Proceedings of the 2000 international symposium on Low power electronics and design, p.90-95, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344526]
• 15: Siddharth Rele , Santosh Pande , Soner Önder , Rajiv Gupta, Optimizing Static Power Dissipation by Functional Units in Superscalar Processors, Proceedings of the 11th International Conference on Compiler Construction, p.261-275, April 08-12, 2002
• 16: Tendler, J. M., Dodson, J. S., Fields, J. S., Le, H., and Sinharoy, B. POWER4 System Microarchitecture. IBM Journal Research and Development 46, 1 (2002).

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Pipeline processors

General Terms:
Design, Performance

Keywords:
execution units, low power, microarchitecture, power-gating