Improved clock-gating through transparent pipelining

ABSTRACT

This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 40-60% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput.

REFERENCES

• 1: David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000 [doi>10.1109/40.888701]
• 2: Anantha P. Chandrakasan , Robert W. Brodersen, Low-Power CMOS Design, Wiley-IEEE Press, 1997
• 3: Anthony Correale, Jr., Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers, Proceedings of the 1995 international symposium on Low power design, p.75-80, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224095]
• 4: EFTHYMIOU, A., AND GARSIDE, J. Adaptive Pipeline Depth Control for Processor Power-Management. In ICCD (2002).
• 5: Michael K. Gowan , Larry L. Biro , Daniel B. Jackson, Power considerations in the design of the Alpha 21264 microprocessor, Proceedings of the 35th annual conference on Design automation, p.726-731, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277226]
• 6: Jinson Koppanalil , Prakash Ramrakhyani , Sameer Desai , Anu Vaidyanathan , Eric Rotenberg, A case for dynamic pipeline scaling, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France [doi>10.1145/581630.581632]
• 7: Hajime Shimada , Hideki Ando , Toshio Shimada, Pipeline stage unification: a low-energy consumption technique for future mobile processors, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871587]
• 8: Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Pipeline processors

General Terms:
Design, Performance

Keywords:
adaptive pipeline depth, circuits, clock gating, dynamic pipeline scaling, high performance, low power, microarchitecture, optimal pipeline clocking, pipeline stage unification, transparent pipeline