Experimental measurement of a novel power gating structure with intermediate power saving mode

ABSTRACT

A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 um CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

REFERENCES

• 1: J.T. et al., "Adaptive body bias for reducing impacts of die-to-die and within die parameter variations on microprocessor frequency and leakage," in Proceedings of International Solid-State Circuits Conference pp. 422--423, 2001.
• 2: K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE vol. 91, pp. 305--327, Feb. 2003.
• 3: S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamda, "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Sold-State Circuits vol. SC-30, pp. 847--854, Aug. 1995.
• 4: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 5: H. Kawaguchi, K. Nose, and T. Sakura, "A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current," IEEE Journal of Solid-State Circuits vol. SC-35, pp. 1498--1501, Oct. 2000.
• 6: Stephen V. Kosonocky , Mike Immediato , Peter Cottrell , Terence Hook , Randy Mann , Jeff Brown, Enchanced multi-threshold (MTCMOS) circuits using variable well bias, Proceedings of the 2001 international symposium on Low power electronics and design, p.165-169, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383125]
• 7: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 8: Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871515]
• 9: S. Kim, S.V. Kosonocky, D.R. Knebel, K. Stawiasz, D. Heidel, and M. Immediato, "Minimizing inductive noise in system-on-a-chip with multiple power gating structures," in Proceedings of European Solid-State Circuits pp. 16--18, 2003.
• 10: Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer, Analysis of Ground Bounce in Deep Sub-Micron Circuits, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.110, April 27-May 01, 1997
• 11: A. Kabbani and A.J. Al-Khalili, "Estimation of ground bounce effects on CMOS circuits," IEEE Transactions on Components and Packaging Technology vol. 22, pp. 316--325, June 1999.
• 12: K.T. Tang and E.G. Friedman, "On-chip ?I noise in the power distribution networks of high speed CMOS integrated circuit," in Proceedings of IEEE International ASIC/SOC Conference pp. 53--57, Sept. 2000.
• 13: Mondira Deb Pant , Pankaj Pant , D. Scott Wills , Vivek Tiwari, An architectural solution for the inductive noise problem due to clock-gating, Proceedings of the 1999 international symposium on Low power electronics and design, p.255-257, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313938]
• 14: Wael El-Essawy , David H. Albonesi , Balaram Sinharoy, A microarchitectural-level step-power analysis tool, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566477]
• 15: K. Kumagai, J. Iwaki, H. Suzuki, T. Yamada, and S. Kurosawa, "A novel powering-down scheme for low Vt CMOS circuits," in Digest of Technical Papers of IEEE Symposium on VLSI Circuits pp. 44--45, 1998.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

General Terms:
Design, Reliability

Keywords:
clock gating, ground bounce, inductive noise, power gating, system-on-a-chip (SOC) design, wake-up latency