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Back-end assignment schemes for clustered multithreaded processors
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International Conference on Supercomputing archive
Proceedings of the 18th annual international conference on Supercomputing table of contents
Malo, France
SESSION: Clustered microarchitectures table of contents
Pages: 316 - 325  
Year of Publication: 2004
ISBN:1-58113-839-3
Authors
Fernando Latorre  Universitat Politècnica de Catalunya, Barcelona
José González  Universitat Politècnica de Catalunya, Barcelona
Antonio González  Universitat Politècnica de Catalunya, Barcelona
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

Power consumption and wire delays are two important limiting factors for current and forthcoming processors. Monolithic designs that keep reasonable power consumption and operate at high clock frequencies are ever harder to implement. In this paper we propose a novel multithreaded clustered microarchitecture that consists of a clustered front-end capable of fetching instructions from multiple hreads and a clustered back-end where instructions are executed. This microarchitecture combines the concepts of multithreading and clustering to a tack both problems: power consumption and wire delays. A key aspect of this microarchitecture is the assignment of resources to the simultaneously running threads. We propose two back-end assignment schemes; in the Static Back-end Assignment (SBA)the back-ends are statically assigned to the front-ends, while in the Dynamic Back-end Assignment (DBA) the back-ends are dynamically assigned according to the demands of each front-end. A limit study of the potential performance of DBA shows a minor benefit compared to SBA. The causes why the DBA scheme does not perform as initially expected are investigated and the main limiting factors of this architecture are evaluated. Finally,we point out he advantages of DBA versus SBA.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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R. Canal, J.M. Parcerisa and A. González. Dynamic Cluster Assignment Mechanisms. In Proceedings of the HPCA-6, 2000.
 
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A. Buyuktosunoglu, P. Bose, P.W. Cook and S.E. Schuster. Tradeoffs in Power-Efficient Issue Queue Design. PACT2000, Nov. 2000.
 
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A. Aggarwal and M. Franklin. An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors. In Proceedings of ISPASS, 2001.
 
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Intel Corp. Intel Pentium 4 Processor. http://www.intel.com/~products/desk_lap/processors/desktop/pentium4/, 2002.
 
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Intel Corp. Hyper-Threading technology. http://www.intel.com/technology/hyperthread/index.htm
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B. Sinharoy "POWER5 Architecture and Systems", Keynote presentation, International Symposium on High Performance Computer Architecture, Feb. 2004.


Collaborative Colleagues:
Fernando Latorre: colleagues
José González: colleagues
Antonio González: colleagues