Performance effects of architectural complexity in the Intel 432

ABSTRACT

The Intel 432 is noteworthy as an architecture incorporating a large amount of functionality that most other systems perform by software. It has, in effect, “migrated” this functionality from the software into the microcode and hardware. The benefits of functional migration have recently been a subject of intense controversy, with critics claiming that a complex architecture is inherently less efficient than a simple architecture with good software support. This paper examines the performance impact of the incorporation of several kinds of functionality into the Intel 432. Among these are the addressing structure, the caches, instruction alignment, the buses, and the way that garbage collection is handled. A set of several benchmarks is used to quantify the performance effect of each of these decisions. The results indicate that the 432 could have been speeded up very significantly if a small number of implementation decisions had been made differently, and if incrementally better technology had been used in its construction. Even with these modifications, however, the 432 would still have only one-fourth to one times the speed of its contemporaries. These figures may represent the real cost of the 432's style of object-based programming environment.

REFERENCES

• 1: BAYLISS, J. A., COLLEY, S. R., KRAVITZ, R. H., MCCORMICK, G. A., RICHARDSON, W. S., WILDE, D. K., AND WITTMER, L. L. The instruction decoding unit for the VLSI 432 general data processor. IEEE J. Solid-State Circuits SC-16, 5 (Oct. 1981), 531-537.
• 2: BAYLISS, J. A., DEETZ, J. A., NG, C. K., OGILVIE, S. A., PETERSON, C. B., AND WILDE, D. K. The interface processor for the Intel VLSI 432 32-bit computer. IEEE J. Solid-State Circuits SC- 16, 5 (Oct. 1981), 522-530.
• 3: Douglas W. Clark, Cache Performance in the VAX-11/780, ACM Transactions on Computer Systems (TOCS), v.1 n.1, p.24-37, Feb. 1983 [doi>10.1145/357353.357356]
• 4: Douglas W. Clark , Joel S. Emer, Performance of the VAX-11/780 translation buffer: simulation and measurement, ACM Transactions on Computer Systems (TOCS), v.3 n.1, p.31-62, Feb. 1985 [doi>10.1145/214451.214455]
• 5: Robert Paul Colwell, The performance effects of functional migration and architectural complexity in object-oriented systems (risc), 1985
• 6: George W. Cox , William M. Corwin , Konrad K. Lai , Fred J. Pollack, Interprocess communication and processor dispatching on the Intel 432, ACM Transactions on Computer Systems (TOCS), v.1 n.1, p.45-66, Feb. 1983 [doi>10.1145/357353.357358]
• 7: David R. Ditzel , David A. Patterson, Retrospective on high-level language computer architecture, Proceedings of the 7th annual symposium on Computer Architecture, p.97-104, May 06-08, 1980, La Baule, United States [doi>10.1145/800053.801914]
• 8: R. S. Fabry, Capability-based addressing, Communications of the ACM, v.17 n.7, p.403-412, July 1974 [doi>10.1145/361011.361070]
• 9: FULLER, S. H., AND BURR, W.E. Measurement and evaluation of alternative computer architectures. Computer (Oct. 1977), 24-35.
• 10: E. F. Gehringer , R. P. Colwell, Fast object-oriented procedure calls: lessons from the Intel 432, Proceedings of the 13th annual international symposium on Computer architecture, p.92-101, June 02-05, 1986, Tokyo, Japan
• 11: Edward F Gehringer , Dan Siewiorek , Zary Segall, Parallel processing: the Cm* experience, Digital Press, Newton, MA, 1986
• 12: Adele Goldberg , David Robson, Smalltalk-80: the language and its implementation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1983
• 13: Paul M. Hansen , Mark A. Linton , Robert N. Mayo , Marguerite Murphy , David A. Patterson, A performance evaluation of the Intel iAPX 432, ACM SIGARCH Computer Architecture News, v.10 n.4, p.17-26, June 1982 [doi>10.1145/641542.641545]
• 14: HENNESSY, J. L. VLSI Processor Architecture. IEEE Trans. Comput. C-33, 12 (Dec. 1984), 1221-1246.
• 15: John Hennessy , Norman Jouppi , Forest Baskett , Thomas Gross , John Gill, Hardware/software tradeoffs for increased performance, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.2-11, March 01-03, 1982, Palo Alto, California, United States
• 16: Dwight D. Hill, An analysis of C machine support for other block-structured languages, ACM SIGARCH Computer Architecture News, v.11 n.4, p.6-16, September 1983 [doi>10.1145/641596.641597]
• 17: INTEL CORPORATION. Introduction to the iAPX 432 Architecture Manual 171821-001, Intel Corporation, Santa Clara, Calif., 1981.
• 18: INTEL CORPORATION. iAPX 432 Object Primer Manual 171858-001, Rev. B. Intel Corporation, Santa Clara, Calif., 1981.
• 19: INTEL CORPORATION. iAPX 432 General Data Processor Architecture Reference Manual, Rev. 3 (Advance Partial Issue) Manual 171860-003, Intel Corporation, Santa Clara, Calif., 1982.
• 20: INTEL CORPORATION. Ada Description of iAPX 432 Microcode Algorithms (Rel. 3). Intel Corporation, Santa Clara, Calif., 1982.
• 21: JOHNSON, D. The Inte1432: a VLSI Architecture for fault-tolerant computer systems. Computer 17, 8 (August 1984), 40-48.
• 22: Anita K. Jones, The Object Model: A Conceptual Tool for Structuring Software, Operating Systems, An Advanced Course, p.7-16, January 1978
• 23: Douglas W. Jones, Systematic protection mechanism design, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.77-80, March 01-03, 1982, Palo Alto, California, United States
• 24: LEVERETT, B. W., CATTEL, R. G. G., HOBBS, S. O., NEWCOMER, J. M., REINER, A. H., SCHATZ, B. R., AND WULF, W.A. An overview of the production quality compiler-compiler project. Computer 13, 8 {Aug. 1980).
• 25: Henry M. Levy, Capability-Based Computer Systems, Butterworth-Heinemann, Newton, MA, 1984
• 26: MUDGE, T. N., BUZZARD, G. D., VERHAEGHE, D. J., HILL, J., AND WINSOR, D.C. Object-based computer architectures. Tech. Rep. CRL-TR-18-83, Dept. of EECS, Univ. of Michigan, April, 1983.
• 27: Elliot I. Organick, A programmer's view of the Intel 432 system, McGraw-Hill, Inc., New York, NY, 1983
• 28: Elliott Irving Organick, Interpreting machines: Architecture and programming of the B1700/B1800 series (Operating and programming systems series), North-Holland, 1978
• 29: David A. Patterson, Reduced instruction set computers, Communications of the ACM, v.28 n.1, p.8-21, Jan. 1985 [doi>10.1145/2465.214917]
• 30: Fred J. Pollack , George W. Cox , Dan W. Hammerstrom , Kevin C. Kahn , Konrad K. Lai , Justin R. Rattner, Supporting ada memory management in the iAPX-432, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.117-131, March 01-03, 1982, Palo Alto, California, United States
• 31: Terence W. Pratt, Programmming languages: design and implementation (2nd ed.), Prentice-Hall, Inc., Upper Saddle River, NJ, 1987
• 32: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• 33: TREDENNICK, N. Future microprocessors. Lecture given at Carnegie-Mellon Univ., Dept. of Computer Science, Pittsburgh, Pa., April 12, 1985.
• 34: Peter Wegner, Dimensions of object-based language design, ACM SIGPLAN Notices, v.22 n.12, p.168-182, Dec. 1987
• 35: Reinhold P. Weicker, Dhrystone: a synthetic systems programming benchmark, Communications of the ACM, v.27 n.10, p.1013-1030, Oct 1984 [doi>10.1145/358274.358283]
• 36: WEICKER, R.P. Execution times for the 'Dhrystone' benchmark program. March 1985. To be published.
• 37: Terry A. Welch, An investigation of descriptor oriented architecture, Proceedings of the 3rd annual symposium on Computer architecture, p.141-146, January 19-21, 1976
• 38: M. V Wilkes, The Cambridge CAP computer and its operating system (Operating and programming systems series), North-Holland, 1979
• 39: WULF, W.A. Compilers and computer architecture. Computer 14, 7 (July 1981), 41-48.
• 40: WULF, W. A., HARBISON, S., AND LEVIN, R. Hydra/C.mmp: An Experimental Computer System. McGraw-Hill, New York, 1981.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.m Miscellaneous

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures
          Subjects: Single-instruction-stream, single-data-stream processors (SISD)**
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**; Multiple-instruction-stream, multiple-data-stream processors (MIMD)
      C.1.3 Other Architecture Styles
          Subjects: Capability architectures**; Stack-oriented processors**; High-level language architectures**

  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Compilers

General Terms:
Design, Measurement, Performance, Security