FPGA power reduction using configurable dual-Vdd

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FPGA power reduction using configurable dual-Vdd

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 41st annual Design Automation Conference table of contents

San Diego, CA, USA

SESSION: FPGA-based systems table of contents

Pages: 735 - 740

Year of Publication: 2004

ISBN:1-58113-828-8

Authors

Fei Li	University of California, Los Angeles, CA
Yan Lin	University of California, Los Angeles, CA
Lei He	University of California, Los Angeles, CA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 45, Citation Count: 20

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ABSTRACT

Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a satisfactory performance and power tradeoff. We design FPGA circuits and logic fabrics using configurable dual-Vdd and develop the corresponding CAD flow to leverage such circuits and logic fabrics. We then carry out a highly quantitative study using area, delay and power models obtained from detailed circuit design and SPICE simulation in 100nm technology. Compared to single-Vdd FPGAs with optimized Vdd level for the same target clock frequency, configurable dual-Vdd FPGAs with full and partial supply programmability for logic blocks reduce logic power by 35.46% and 28.62% respectively and reduce total FPGA power by 14.29% and 9.04% respectively. To the best of our knowledge, it is the first in-depth study on FPGAs with configurable dual-Vdd for power reduction.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 20

	Yu Hu , Yan Lin , Lei He , Tim Tuan, Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Jingzhao Ou , Viktor K. Prasanna, A cooperative management scheme for power efficient implementations of real-time operating systems on soft processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.1, p.45-56, January 2008
	Yan Lin , Yu Hu , Lei He , Vijay Raghunat, An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Yan Lin , Fei Li , Lei He, Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yan Lin , Lei He, Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004
	Lerong Cheng , Phoebe Wong , Fei Li , Yan Lin , Lei He, Device and architecture co-optimization for FPGA power reduction, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Suresh Srinivasan , A. Gayasen , N. Vijaykrishnan , T. Tuan, Leakage control in FPGA routing fabric, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yan Lin , Fei Li , Lei He, Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Chi-Feng Li , Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang, Post-placement leakage optimization for partially dynamically reconfigurable FPGAs, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	David Lewis , Elias Ahmed , David Cashman , Tim Vanderhoek , Chris Lane , Andy Lee , Philip Pan, Architectural enhancements in Stratix-III™ and Stratix-IV™, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
	Deming Chen , Jason Cong , Yiping Fan , Junjuan Xu, Optimality study of resource binding with multi-Vdds, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal module and voltage assignment for low-power, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	J. H. Anderson , F. N. Najm, Low-power programmable routing circuitry for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.602-609, November 07-11, 2004
	Rajarshi Mukherjee , Seda Ogrenci Memik, Evaluation of dual V_DD fabrics for low power FPGAs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Tim Tuan , Sean Kao , Arif Rahman , Satyaki Das , Steve Trimberger, A 90nm low-power FPGA for battery-powered applications, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006
	Rajarshi Mukherjee , Song Liu , Seda Ogrenci Memik , Somsubhra Mondal, A high-level clustering algorithm targeting dual V_dd FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008
	Qiang Wang , Subodh Gupta , Jason H. Anderson, Clock power reduction for virtex-5 FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
	Yu Hu , Yan Lin , Lei He , Tim Tuan, Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.2, p.1-29, April 2008