Designing robust microarchitectures

ABSTRACT

A fault-tolerant approach to microprocessor design, developed at the University of Michigan, is presented. Our approach is based on the use of in-situ checker components that validate the functional and electrical characteristics of complex microprocessor designs. Two design techniques are highlighted: a low-cost double-sampling latch design capable of eliminating power-hungry voltage margins, and a formally verifiable checker co-processor that validates all computation produced by a complex microprocessor core. By adopting a "better than worst-case" approach to system design, it is possible to address reliability and uncertainty concerns that arise during design, manufacturing and system operation.

REFERENCES

• 1: Todd Austin , David Blaauw , Trevor Mudge , Krisztián Flautner, Making Typical Silicon Matter with Razor, Computer, v.37 n.3, p.57-65, March 2004 [doi>10.1109/MC.2004.1274005]
• 2: Chris Weaver , Todd M. Austin, A Fault Tolerant Approach to Microprocessor Design, Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS), p.411-420, July 01-04, 2001

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Reliability

Keywords:
computer system design, low-power, microarchitecture, reliable microarchitecture design, system-on-a-chip