Reliable communication in systems on chips

ABSTRACT

System on Chip (SoC) design faces several challenges which are due to the extremely small nature of electronic devices and the consequent opportunity to realize multi-processing systems of extremely high complexity. To manage large scale design, SoCs are assembled out of complex standard parts, such as programmable cores and memory arrays. Thus, the major design challenge is to provide correct and reliable operation of the interconnected components. Top-down correct component interconnection will become increasingly harder to succeed, because the interface features of components will also scale-up in complexity. New design methodologies will need to leverage component self-configuration and adaptation to the underlying communication fabric.

REFERENCES

• 1: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 2: D. Bertozzi , L. Benini , G. de Micheli, Low Power Error Resilient Encoding for On-Chip Data Buses, Proceedings of the conference on Design, automation and test in Europe, p.102, March 04-08, 2002
• 3: William J. Dally , Brian Towles, Route packets, net wires: on-chip inteconnectoin networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 4: K. Goossens , P. Wielage , A. Peeters , J. Van Meerbergen, Networks on Silicon: Combining Best-Effort and Guaranteed Services, Proceedings of the conference on Design, automation and test in Europe, p.423, March 04-08, 2002
• 5: Pierre Guerrier , Alain Greiner, A generic architecture for on-chip packet-switched interconnections, Proceedings of the conference on Design, automation and test in Europe, p.250-256, March 27-30, 2000, Paris, France [doi>10.1145/343647.343776]
• 6: Antoine Jalabert , Srinivasan Murali , Luca Benini , Giovanni De Micheli, ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip, Proceedings of the conference on Design, automation and test in Europe, p.20884, February 16-20, 2004
• 7: A Network on Chip Architecture and Design Methodology, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, p.117, April 25-26, 2002
• 8: Frédéric Worm , Paolo Ienne , Patrick Thiran , Giovanni De Micheli, An adaptive low-power transmission scheme for on-chip networks, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan [doi>10.1145/581199.581221]
• 9: Terry Tao Ye , Luca Benini , Giovanni De Micheli, Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.81-104, February 2004 [doi>10.1016/j.sysarc.2003.07.005]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Reliability

Keywords:
SoCs, VLSI, networking