A communication-theoretic design paradigm for reliable SOCs

ABSTRACT

Presented is a design paradigm, pioneered at the University of Illinois in 1997, for reliable and energy-efficient system-on-a-chip (SOC) in nanometer process technologies. These technologies are characterized by non-idealities such as coupling, leakage, soft errors, and process variations, which contribute to a reliability problem. Increasing complexity of systems-on-a-chip (SOC) leads to a related power problem. The proposed paradigm provides solutions to both problems by viewing SOCs as communication networks, and employs ideas from error-control coding, communications, and information theory in order to achieve the dual goals of reliability and energy-efficiency.

REFERENCES

• 1: N. R. Shanbhag, "A mathematical basis for power-reduction in digital VLSI systems," IEEE Trans. on Circuits and Systems, Part II, vol. 44, no. 11, pp. 935--951, Nov. 1997.
• 2: Naresh R. Shanbhag, Reliable and Efficient System-on-Chip Design, Computer, v.37 n.3, p.42-50, March 2004 [doi>10.1109/MC.2004.1274003]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Algorithms, Reliability

Keywords:
coding, communications, low-power, reliability, system-on-a-chip