Optimization of a digital neuron design

ABSTRACT

Artificial neural network models, composed of many non-linear processing elements operating in parallel, have been extensively simulated in software. The real estate required for neurons and their interconnections has been the major hindrance for hardware implementation. Therefore, a reduction in neuron size is highly advantageous. A digital neuron design consisting of an arithmetic logic unit (ALU) has been implemented to conform to the hard-limiting threshold function. Studies on reducing the ALU size, utilizing Monte-Carlo simulations, indicate that its effect on network reliability and efficiency is not detrimental. Neurons with reduced ALU size operate with the same computational abilities as full sized neurons.

REFERENCES

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Arithmetic and logic units

  D. Software
  D.2 SOFTWARE ENGINEERING

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
  I.6 SIMULATION AND MODELING

General Terms:
Design, Performance, Reliability