Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage

ABSTRACT

Path delay fault testing becomes increasingly important due tohigher clock rates and higher process variability caused by shrinkinggeometries. Achieving high-coverage path delay fault testingrequires the application of scan justified test vector pairs, coupledwith careful ordering of the scan flip-flops and/or insertion ofdummy flip-flops in the scan chain. Previous works on scan synthesisfor path delay fault testing using scan shifting have focusedexclusively on maximizing fault coverage and/or minimizing thenumber of dummy flip-flops, but have disregarded the scan wirelengthoverhead. In this paper we consider both dummy flip-flopand wirelength costs, and focus on post-layout formulations thatcapture the achievable tradeoffs between these costs and delay faultcoverage in scan chain synthesis.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Placement and routing

General Terms:
Algorithms, Design, Performance