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A Theory of Non-Deterministic Networks
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Source International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents
Page: 709  
Year of Publication: 2003
ISBN ~ ISSN:1092-3152 , 1-58113-762-1
Authors
Alan Mishchenko  University of California at Berkeley
Robert K. Brayton  University of California at Berkeley
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Citation Count: 1
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DOI Bookmark: 10.1109/ICCAD.2003.22

ABSTRACT

Both non-determinism and multi-level networks compactlycharacterize the flexibility allowed in implementing a circuit.A theory for representing and manipulating non-deterministic(ND) multi-level networks is developed. The theory supports allthe network manipulations commonly applied to deterministicbinary networks, such as node minimization, elimination, anddecomposition. It is shown that an ND network's behavior can beinterpreted in three ways, all of which coincide when the networkis deterministic. Operations performed on an ND network areanalyzed under each interpretation for changes in a network'sbehavior. Modifications of a few operations are given which mustbe used to guarantee that a network's behavior does not violateits external specification. These modifications depend on whichbehavior is being used and the location of related non-determinism.This theory has been implemented in a system,MVSIS. We provide comparisons among the uses of the various behaviors.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[3] A. Mishchenko, and R. Brayton, "A Boolean paradigm for multivalued logic synthesis", Proc. IWLS'02, June, 2002, pp. 173-177.
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[5] A. Mishchenko, and R. Brayton, "A Theory of Non-Deterministic Networks", UC Berkeley Tech. Rep., ERL, EECS Dept., Feb. 2003.
 
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[6] MVSIS Group. MVSIS. UC Berkeley. http://www-cad.eecs.berkeley.edu/mvsis/
 
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[7] R. L. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization". IEEE Trans. CAD, Vol. 6(5), pp. 727-750, Sep. 1987.
 
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[8] E. Sentovich, et al, "SIS: A system for sequential circuit synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.
 
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[9] Y. Watanabe, L. Guerra and R. K. Brayton, "Logic optimization with multi-output gates", Proc. ICCD '93, pp. 416-420.
 
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Collaborative Colleagues:
Alan Mishchenko: colleagues
Robert K. Brayton: colleagues