ACM Home Page
Please provide us with feedback. Feedback
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level
Full text PdfPdf (211 KB)
Source International Conference on Computer Aided Design archive
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design table of contents
Page: 693  
Year of Publication: 2003
ISBN ~ ISSN:1092-3152 , 1-58113-762-1
Authors
Yuvraj Singh Dhillon  Georgia Institute of Technology, Atlanta, GA
Abdulkadir Utku Diril  Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee  Georgia Institute of Technology, Atlanta, GA
Hsien-Hsin Sean Lee  Georgia Institute of Technology, Atlanta, GA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 17,   Citation Count: 7
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: 10.1109/ICCAD.2003.27

ABSTRACT

This paper proposes an optimum methodology forassigning supply and threshold voltages to modules in a CMOScircuit such that the overall energy consumption is minimizedfor a given delay constraint. The modules of the circuit shouldhave large enough gate depths such that the delay and energypenalties of the level shifters connecting them are negligible.Both static and dynamic energy are considered in theoptimization. Energy savings of up to 48% have been achievedon various example circuits. The first step in the optimizationfinds optimum supply and threshold voltages for each modulein the circuit. If the circuit has a large number of modules, thisstep might yield a correspondingly large number of differentsupply and threshold voltages for minimum energyconsumption. Since having a large number of different supplyand threshold voltages on an IC is not feasible in currenttechnologies, an additional step clusters the multiple voltagesobtained from the first step into a fixed number of supply andthreshold voltages (for example, 2 different supply voltagesand 2 different threshold voltages). In addition to theapplication of this method to circuit optimization, it can also beapplied to a wide range of problems with delay constraints,such as software tasks running on a dynamically variable V{DD}and V{th} processor.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
[2] T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, pp. 584-594, April 1990.
3
4
 
5
 
6
 
7
8
 
9
[9] Y. Moisiadis, I. Bouras, A. Arapoyanni, "Dynamic back bias CMOS driver for low-voltage applications," Electronics Letters, vol. 36, no. 2, pp. 135-136, Jan. 2000.
10
 
11
[11] K. Nose, T. Sakurai, "Analysis and future trend of short-circuit power," IEEE Trans. on CAD, vol. 19, no. 9, pp. 1023-1030, Sept. 2000.
 
12
 
13
[13] R. Nair, C.L. Berman, P.S. Hauge, E.J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. on CAD, vol. 8, no. 8, pp. 860-874, Aug. 1989.
14
 
15
 
16

CITED BY  7
 

Collaborative Colleagues:
Yuvraj Singh Dhillon: colleagues
Abdulkadir Utku Diril: colleagues
Abhijit Chatterjee: colleagues
Hsien-Hsin Sean Lee: colleagues