A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

ABSTRACT

Input vector control has been used to minimize the leakage powerconsumption of a circuit in sleep state. In this paper, we presenta novel heuristic for determining a low leakage vector to beapplied to a circuit in sleep state. The heuristic is a greedy searchbased on the controllability of nodes in the circuit and uses thefunctional dependencies among cells in the circuit to guide thesearch. Results on a set of ISCAS and MCNC benchmark circuitsshow that in all cases our heuristic returns a vector having aleakage within 5% of that of the vector obtained using an extensiverandom search, with orders of magnitude improvement incomputational speed.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Heuristic methods

General Terms:
Algorithms, Performance