Performance Efficiency of Context-Flow System-on-Chip Platform

ABSTRACT

Recent efforts in adapting computer networks into system-on-chip(SOC), or network-on-chip, present a setback to the traditionalcomputer systems for the lack of effective programming model,while not taking full advantage of the almost unlimited on-chipbandwidth. In this paper, we propose a new programming model,called context-flow, that is simple, safe, highly parallelizable yettransparent to the underlying architectural details. An SOC platformarchitecture is then designed to support this programmingmodel, while fully exploiting the physical proximity between theprocessing elements. We demonstrate the performance efficiencyof this architecture over bus based and packet-switch based networksby two case studies using a multi-processor architecture simulator.

REFERENCES

• 1: [1] Mark Horowitz, Ron Ho, and Ken Mai, "The future of wires," in Proceedings of the IEEE, April 2001, pp. 490- 504.
• 2: William J. Dally , Brian Towles, Route packets, not wires: on-chip inteconnection networks, Proceedings of the 38th conference on Design automation, p.684-689, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379048]
• 3: [3] http://www.systemc.org.
• 4: [4] D. Gajski, J. Zhu, D. Doemer, A. Gerstlauer, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, Boston, March 2000.
• 5: [5] http://www-unix.mcs.anl.gov/mpi.
• 6: [6] OMG Web Site, http://www.omg.org/.
• 7: [7] Doug Burger and Todd M. Austin, "The Simple Scalar tool set, version 2.0," Tech. Rep., Computer Science Department, University of Wisconsin, 1997.
• 8: [8] Rudolf Usselmann, "DES/Triple DES IP cores," September 2001.
• 9: Bruce Schneier, Applied cryptography (2nd ed.): protocols, algorithms, and source code in C, John Wiley & Sons, Inc., New York, NY, 1995
• 10: Elliot Waingold , Michael Taylor , Devabhaktuni Srikrishna , Vivek Sarkar , Walter Lee , Victor Lee , Jang Kim , Matthew Frank , Peter Finch , Rajeev Barua , Jonathan Babb , Saman Amarasinghe , Anant Agarwal, Baring It All to Software: Raw Machines, Computer, v.30 n.9, p.86-93, September 1997 [doi>10.1109/2.612254]
• 11: Jingcao Hu , Radu Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proceedings of the conference on Design, Automation and Test in Europe, p.10688, March 03-07, 2003
• 12: [12] David Patterson, Thomas Anderson, Neal Cardwell, Rich ard Fromm, Kimberley Keeton, Christoforos Kozyrakis, Randi Thomas, and Kathy Yelick, "Intelligent RAM (IRAM): Chips that remember and compute," in IEEE International Solid-State Circuits Conference, February 1997.
• 13: Drew Wingard, Micronetwork-based integration for SOCs: 673, Proceedings of the 38th conference on Design automation, p.677, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379046]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design
          Subjects: Network topology

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.4 Parallel Architectures
          Subjects: Mobile processors

General Terms:
Algorithms, Design, Performance