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Cycle-accurate power analysis for multiprocessor systems-on-a-chip
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 14th ACM Great Lakes symposium on VLSI table of contents
Boston, MA, USA
POSTER SESSION: Poster session 2 table of contents
Pages: 410 - 406  
Year of Publication: 2004
ISBN:1-58113-853-9
Authors
Mirko Loghi  University of Verona, Verona, Italy
Massimo Poncino  University of Verona, Verona, Italy
Luca Benini  University of Bologna, Bologna, Italy
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 13,   Downloads (12 Months): 71,   Citation Count: 7
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ABSTRACT

Developing energy-aware software for multiprocessor systems-on-chip (MPSoCs) is a difficult task, which requires the knowledge of the distribution of the power consumption among several heterogeneous devices (cores, memories, busses, etc.). In this work we analyze the power breakdowns of power consumption for a complete MPSoC platform, under several application workloads and operating conditions. We leverage a complete-system simulation platform with accurate power models for all key hardware modules. Our analysis shows that caches and system interconnect dominate in the power breakdown, pointing out how software locality is meaningful not only for performance but also for energy optimization.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  7
 
 

Collaborative Colleagues:
Mirko Loghi: colleagues
Massimo Poncino: colleagues
Luca Benini: colleagues

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