Fault simulation and random test generation for speed-independent circuits

ABSTRACT

We develop a fault simulator for input stuck-at faults in Speed-Independent circuits by extending Eichelberger's method. In order to achieve higher accuracy, a 13-valued algebra is adopted, the relative order of causal signal transitions is maintained, and time frames are unfolded in a careful manner. Based on this simulator, we propose a random test generation algorithm which reduces the probability that the circuit finds itself in non-deterministic states and helps it recover when this happens. Experimental results show that the combination of the two techniques achieves an average improvement of 18% in fault coverage.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.3 Reliability and Testing**

General Terms:
Algorithms, Reliability, Verification

Keywords:
asynchronous circuits, fault simulation, random test pattern generation, speed-independent circuits