Fault secureness need for next generation high performance microprocessor design for testability structures

ABSTRACT

We analyze the risks associated with faults affecting some Design For Testability (DFT) features employed within todays' high performance microprocessors. We will show that, because of the occurrence of internal faults, some of these structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the Fault Secure property, that is well known for Self-Checking Circuits, for DFT structures. We will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults affecting the employed DFT structures. We will discuss the Fault Secureness of the considered DFT structures. We will provide some examples of how the non Fault Secure ones can be modified to meet the Fault Secure goal, thus avoiding their prospected detrimental effect on next generation high performance microprocessors test effectiveness and quality.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

General Terms:
Design, Performance, Reliability

Keywords:
built in self test, comparator, design for testability, fault secureness, microprocessor