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Circuit emulation services over ethernet-part 1: clock synchronization using timestamps
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Source International Journal of Network Management archive
Volume 14 ,  Issue 1  (January 2004) table of contents
Pages: 29 - 44  
Year of Publication: 2004
ISSN:1099-1190
Authors
James Aweya  Nortel Networks, PO Box 3511, Station C, Ottawa, Canada K1Y 4H7
Michel Ouellette
Delfin Y. Montuno
Kent Felske
Publisher
John Wiley & Sons, Inc.  New York, NY, USA
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DOI Bookmark: 10.1002/nem.505

ABSTRACT

Due to Ethernet's ubiquity, simplicity, scalability and cost effectiveness there is significant customer demand for Ethernet-based access and transport in the metropolitan network. Many service providers have recognized this need and are currently establishing Ethernet-based services to meet this demand. The migration to all-Ethernet access will not be instantaneous since many customers currently have legacy TDM access interfaces on their routers and PBX equipment. Circuit Emulation Services (CES) over Ethernet provides TDM circuit emulation to support TDM traffic such as T1/E1, T3/E3, OC3/12, etc. This two-part paper presents the application of CES over Ethernet as well as a new technology that addresses the issues associated with clock recovery and synchronization in an Ethernet network with its inherent network jitter. Part 1 describes a clock synchronization technique where a transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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2. http://www.ietf.org/html.charters/pwe3- charters.html.
 
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3. http://www.metroethernetforum.org.
 
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4. http://www.ieee.org/groups/802/3/efm.
 
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5. Lau RC, Fleischer PE. Synchronous techniques for timing recovery in BISDN. IEEE Trans. Communications 1995;43(2/3/4):1810-1818.
 
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6. ATM Forum af-vtoa-0078.000. Circuit emulation service interoperability specification version 2.0. January 1997.
 
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7. Lindsey WC, Chie CM. A survey of digital phase-locked loops. Proc. IEEE, 1981;69(4):410-431.
 
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8. Best RE. Phase-locked loops. Design, simulation, and applications. Fourth Edition. 1999; McGraw-Hill.


Collaborative Colleagues:
James Aweya: colleagues
Michel Ouellette: colleagues
Delfin Y. Montuno: colleagues
Kent Felske: colleagues

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