Defect tolerance for nanocomputer architecture

ABSTRACT

Defect tolerant architectures will be mandatory for building economical and cheap computing systems with billions of devices of nanometer dimension because it will contain significant number of defects due to statistical variations. The basic idea behind a defect tolerant custom configurable system is to build the system out of partially perfect components, detect the defects and configure the available good resources using software. In this paper we discuss implications of defect tolerance on power, area, delay and other relevant parameters for computing architectures. The additional requirement of a scalable configuration mechanism, redundant components and detection scheme necessitates extra burden on the interconnect to sustain it. Through back-of-envelope calculations using a priori wire length estimation and intuitive arguments we will illustrate the hidden cost of supporting such an architecture.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays
  B.8 Performance and Reliability
      B.8.1 Reliability, Testing, and Fault-Tolerance

  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Fault tolerance

General Terms:
Design, Economics, Performance, Reliability, Theory

Keywords:
FPGA, Rent's rule, defect tolerance, nanocomputing, nanoelectronics, reconfigurability, reliability, wire length estimation