A low power approach to system level pipelined interconnect design

ABSTRACT

System on Chip interconnects require first-in first-out buffers (FIFOs) to handle different data rates between IP cores. The design of an interconnect channel containing multiple stages of FIFO require making tradeoff between throughput and power consumption. The design variables are the sizes of the FIFOs, their voltages and their clock frequencies. Decreasing the FIFO clock frequencies saves power but it causes the channel performance (throughput) to decrease. In this work, we recover the performance by resizing the FIFOs in the channel. The voltage and clock scaling in the interconnect channel followed by FIFO resizing approach leads to significant power savings. The power savings is a function of system parameters λ (expected data production rate) and μ (expected data consumption rate). We observed a maximum dynamic power savings of 45.8%, 28.9% and 11.3% for min(λ, μ) of 0.2, 0.5 and 0.8 respectively. Our approach of reducing voltage in the interconnect channel will reduce the leakage power as well.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)

General Terms:
Design

Keywords:
low power, pipelined interconnect, voltage scaling