| Rapid prototyping using high density interconnects |
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European Design Automation Conference
archive
Proceedings of the conference on European design automation
table of contents
Glasgow, Scotland
SESSION: Selected topics in CAD systems
table of contents
Pages: 439 - 443
Year of Publication: 1990
ISBN:0-8186-2024-2
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Authors
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Richard Hartley
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General Electric CRD, Schenectady, N.Y.
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Kenneth Welles, II
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General Electric CRD, Schenectady, N.Y.
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Michael Hartman
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General Electric CRD, Schenectady, N.Y.
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Paul Delano
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General Electric CRD, Schenectady, N.Y.
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Abhijit Chatterjee
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General Electric CRD, Schenectady, N.Y.
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IEEE Computer Society Press
Los Alamitos, CA, USA
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 1
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ABSTRACT
This paper introduces the (DIODES) system for the rapid prototyping of DSP electronic systems. DIODES merges silicon compiler and high-density interconnect technology with the goal of prototyping hardware systems as quickly as possible --- within one day. Working from a high-level algorithmic description of a DSP algorithm, DIODES will determine which chips from an inventory of specially designed chips are needed to implement the design. These chips are then placed on a prepared substrate and routed together using computer controlled laser lithography to produce a hardware implementation of the design.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. E. Casavant , M. A. d'Abreu , M. Dragomirecky , D. A. Duff , J. R. Jasica , M. J. Hartman , K. S. Hwang , W. D. Smit, A Synthesis Environment for Designing DSP Systems, IEEE Design & Test, v.6 n.2, p.35-44, March 1989
[doi> 10.1109/54.19133]
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{Carlson} Carlson, R. O., Eichelberger, C. W., Wojnarowski, R. J., Levinson, L. M. and Kohl, J. E. A High Density Copper/Polyimide Overlay Interconnection. Proc International Electronics Packaging Conference. (Nov 1988)
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{Chat} Chatterjee, A. and Hartley, R., A New simultaneous circuit partitioning and chip placement approach based on simultaneous annealing. submitted for publication.
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{DIODES2} Welles et. al. A Systematic Hardware-based Approach for Efficient Testing of Hybrid VLSI. Submitted for publication.
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{HC2} Hartley, R. and Corbett, P., A digit serial compiler library. Proc Int. Sym. Circuits and Systems --- ISCAS-89 (1989)
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{JNHH} Jasica, J. R., Noujaim, S., Hartley, R., and Hartman, M. J., A Bit-Serial Silicon Compiler, Proc. of the IEEE Int'l Conf. on Computer-Aided Design, pp. 91--93. (1985)
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{YG} Yassa, F. F. et. al. A multichannel digital demodulator for LVDT and RVDT position sensors. Proc. Custom Integrated Circuits Conference, 1989.
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