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ABSTRACT
Picasso is prototype leaf cell synthesis system capable of mapping a gate level description into a complete set of layout masks, based on the line of diffusion layout style. This paper describes Picasso's algorithms for transistor placement and routing of internal nets. The transistor placement algorithm uses a composite metric which applies connectivity and optimal chaining considerations simultaneously. The routing algorithm is capable of routing over transistor chains and makes efficient use of residual routing areas resulting from unequal transistor sizes.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY
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Chi-Yi Hwang , Yung-Ching Hsieh , Youn-Long Lin , Yu-Chin Hsu, An efficient layout style for 2-metal CMOS leaf cells and their automatic generation, Proceedings of the 28th conference on ACM/IEEE design automation, p.481-486, June 17-22, 1991, San Francisco, California, United States
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