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Transistor placement and interconnect algorithms for leaf cell synthesis
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Source European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents
Glasgow, Scotland
SESSION: Cell generators table of contents
Pages: 119 - 123  
Year of Publication: 1990
ISBN:0-8186-2024-2
Authors
Martin Lefebvre  Carleton University, Ottawa, Canada
Chong Chan  Carleton University, Ottawa, Canada
Grant Martin  Bell-Northern Research, Station C, Ottawa, Canada
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
: EDAC Association
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 7,   Citation Count: 1
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ABSTRACT

Picasso is prototype leaf cell synthesis system capable of mapping a gate level description into a complete set of layout masks, based on the line of diffusion layout style. This paper describes Picasso's algorithms for transistor placement and routing of internal nets. The transistor placement algorithm uses a composite metric which applies connectivity and optimal chaining considerations simultaneously. The routing algorithm is capable of routing over transistor chains and makes efficient use of residual routing areas resulting from unequal transistor sizes.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Uehara, T., vanCleemput, W. M., "Optimal Layout of CMOS Functional Arrays", IEEE Trans. on Computers, vol. c-30, no. 5, May 1981, pp. 305--312.
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3
Nair, R., Bruss, A., Reif, J., "Linear Time Algorithms For Optimal CMOS Layout", in VLSI: Algorithms and Architectures, Bertollazi and Luccio Eds, North-Holland Pub., 1985, pp. 327--338.
 
4
Mailhot, F., DeMicheli, G., "Automatic Layout and Optimization of Static CMOS Cells", Proc. International Conf. on Computer Design, 1988, pp. 180--185.
 
5
Chen, C. Y. R., Hou, C. Y., "A new layout optimization methodology for CMOS complex gates", in Proc. Int. Conf. on Computer-Aided Design, 1988, pp. 368--371.
 
6
Kwon, Y. J., Kyung, C. M., "A fast heuristics for optimal CMOS functional cell layout generation", in Proc. Int. Symposium on Circuits and Systems, 1988, pp. 2423--2426.
 
7
Wimer, S., Pinter, R. Y., Feldman, J. A., "Optimal Chaining of CMOS Transistors in a Functional Cell", IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No.5, September 1987, pp. 795--801.
 
8
Hill, D. D., "Sc2: A Hybrid Automatic Layout System", Proc. International Conference On Computer-Aided Design, 1985, pp. 172--174.
 
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10
Stauffer, A., Nair, R., "Optimal CMOS Cell Transistor Placement: A Relaxation Approach", Proc. International Conference on Computer-Aided Design, 1988, pp. 364--367.
 
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12
Shiple, T., Kollaritsh, P., Smith, D., Allen, J., "Area Evaluation Metrics for Transistor Placement", in Proc. Int. Conf. on Computer Design, 1988, pp. 428--433.
 
13
Kollarritsch, P. W., Weste, N. H. E., "TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout", IEEE Journal of Solid-State Circuits, vol. SC-20, no. 3, June 1985, pp. 799--804.
 
14
Kollarritsch, P. W., Lusky, S., Prasad, S., Potter, N., "CLAY: A Malleable-cell Multi-cell Transistor Matrix Approach for CMOS LAYout Synthesis", in Proc. Int. Conf. on Computer-Aided Design, 1988, pp. 142--145.
 
15
Kim, J. H., McDermott, J., Siewiorek, D. P., "Exploiting Domain Knowledge in IC Cell Layout", IEEE Design and Test, August 1984, pp. 52--64.
 
16
Lefebvre, M. C., Chan, C. H., "Flexible Boundaries for Layout Synthesis", Proc. VLSI'89 International Conference, August 1989.
 
17
Lefebvre, M. C., Chan, C. H., "Optimal ordering of gate signals in CMOS complex gates", in Proc. Int. Custom Integrated Circuits Conf., 1989.
 
18
Lefebvre, M. C., CMOS Leaf Cell Synthesis, Ph.D. Dissertation, Dept. of Electronics, Carleton University, April 1989.

Collaborative Colleagues:
Martin Lefebvre: colleagues
Chong Chan: colleagues
Grant Martin: colleagues