Multimode scan: Test per clock BIST for IP cores

ABSTRACT

Built-in self-test (BIST) is an attractive design-for-test methodology for core-based SoC design because of the minimal need for test access when tests are generated and evaluated within the core itself. However, the scan based logic BIST approach being widely considered for this application suffers from two significant weaknesses: slow test-per-scan execution, and a limited capability for detecting realistic timing and delay faults, critical in deep submicron technologies. The new multimode scan based approach presented here supports test-per-clock BIST, which runs orders of magnitude faster, and also provides significantly better delay fault coverage.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.2 Reliability and Testing**

General Terms:
Design

Keywords:
BIST, SoC, digital testing, scan