Test data compression using dictionaries with selective entries and fixed-length indices

ABSTRACT

We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive a large number of internal scan chains in the circuit under test. Therefore, it is especially suitable for a reduced pin-count and low-cost DFT test environment, where a narrow interface between the tester and the SOC is desirable. The dictionary-based approach not only reduces test data volume but it also eliminates the need for additional synchronization and handshaking between the SOC and the ATE. The dictionary entries are determined during the compression procedure by solving a variant of the well-known clique partitioning problem from graph theory. Experimental results for the ISCAS-89 benchmarks and representative test data from IBM show that the proposed method outperforms a number of recently-proposed test data compression techniques. Compared to the previously proposed test data compression approach based on selective Huffman coding with variable-length indices, the proposed approach generally provides higher compression for the same amount of hardware overhead.

REFERENCES

• 1: Carl Barnhart , Vanesa Brunkhorst , Frank Distler , Owen Farnsworth , Brion L. Keller , Bernd Koenemann , Andrej Ferko, OPMISR: the foundation for compressed ATPG vectors, Proceedings of the IEEE International Test Conference 2001, p.748-757, October 30-November 01, 2001
• 2: Ismet Bayraktaroglu , Alex Orailoglu, Test volume and application time reduction through scan chain concealment, Proceedings of the 38th conference on Design automation, p.151-155, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378388]
• 3: Anshuman Chandra , Krishnendu Chakrabarty, Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression, Proceedings of the 19th IEEE VLSI Test Symposium, p.42, March 29-April 03, 2001
• 4: Chandra, A. and Chakrabarty, K. 2001b. System-on-a-chip test data compression and decompression architectures based on Golomb codes. IEEE Trans. Computer-Aided Design 20, 355--368.
• 5: Thomas H. Cormen , Clifford Stein , Ronald L. Rivest , Charles E. Leiserson, Introduction to Algorithms, McGraw-Hill Higher Education, 2001
• 6: El-Maleh, A. and Al-Abaji, R. 2002. Extended frequency-directed run-length codes with improved application to system-on-a-chip test data compression. In Proceedings of the International Conference on Electronics, Circuits and Systems. 449--452.
• 7: Aiman El-Maleh , Ali Al-Suwaiyan, An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits, Proceedings of the 20th IEEE VLSI Test Symposium, p.53, April 28-May 02, 2002
• 8: Aiman El-Maleh , Esam Khan , Saif al Zahir, A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip, Proceedings of the 19th IEEE VLSI Test Symposium, p.54, March 29-April 03, 2001
• 9: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• 10: P. Gonciari , B. Al-Hashimi , N. Nicolici, Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression, Proceedings of the conference on Design, automation and test in Europe, p.604, March 04-08, 2002
• 11: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
• 12: Sybille Hellebrand , Hua-Guo Liang , Hans-Joachim Wunderlich, A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS, Proceedings of the 2000 IEEE International Test Conference, p.778, October 03-05, 2000
• 13: Frank F. Hsu , Kenneth M. Butler , Janak H. Patel, A case study on the implementation of the Illinois Scan Architecture, Proceedings of the IEEE International Test Conference 2001, p.538-547, October 30-November 01, 2001
• 14: Vikram Iyengar , Krishnendu Chakrabarty , Brian T. Murray, Deterministic Built-in Pattern Generation for Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.97-114, August-October 1999 [doi>10.1023/A:1008384201996]
• 15: Abhijit Jas , Jayabrata Ghosh-Dastidar , Nur A. Touba, Scan Vector Compression/Decompression Using Statistical Coding, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.114, April 26-30, 1999
• 16: Abhijit Jas , Nur A. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, Proceedings of the 1998 IEEE International Test Conference, p.458-464, October 18-22, 1998
• 17: Seiji Kajihara , Kohei Miyase, On identifying don't care inputs of test patterns for combinational circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
• 18: Bernd Koenemann , Carl Barnhart , Brion Keller , Tom Snethen , Owen Farnsworth , Donald Wheater, A SmartBIST Variant with Guaranteed Encoding, Proceedings of the 10th Asian Test Symposium, p.325, November 19-21, 2001
• 19: Januz Rajki , Jerzy Tyzer , Mark Kassab , Nilanjan Mukherjee , Rob Thompson , Kun-Han Tsai , Andre Hertwig , Nagesh Tamarapalli , Grzegorz Mrugalski , Geir Eide , Jun Qian, Embedded Deterministic Test for Low-Cost Manufacturing Test, Proceedings of the 2002 IEEE International Test Conference, p.301, October 07-10, 2002
• 20: S. Reda , A. Orailoglu, Reducing Test Application Time Through Test Data Mutation Encoding, Proceedings of the conference on Design, automation and test in Europe, p.387, March 04-08, 2002
• 21: Sudhakar M. Reddy , Kohei Miyase , Seiji Kajihara , Irith Pomeranz, On Test Data Volume Reduction for Multiple Scan Chain Designs, Proceedings of the 20th IEEE VLSI Test Symposium, p.103, April 28-May 02, 2002
• 22: David Salomon , D. Salomon, Data Compression: The Complete Reference, Springer-Verlag New York, Inc., Secaucus, NJ, 2000
• 23: Schafer, L., Dorsch, R., and Wunderlich, H.-J. 2002. Respin++---Deterministic embedded test. In Proceedings of the European Test Workshop. 37--44.
• 24: Nur A. Touba , Edward J. McCluskey, Altering a Pseudo-Random Bit Sequence for Scan-Based BIST, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.167-175, October 20-25, 1996
• 25: Erik H. Volkerink , Ajay Khoche , Subhasish Mitra, Packet-Based Input Test Data Compression Techniques, Proceedings of the 2002 IEEE International Test Conference, p.154, October 07-10, 2002
• 26: Harald Vranken , Tom Waayers , hervá Fleury , David Lelouvier, Enhanced reduced pin-count test for full-scan design, Proceedings of the IEEE International Test Conference 2001, p.738-747, October 30-November 01, 2001
• 27: Francis G. Wolff , Chris Papachristou, Multiscan-Based Test Compression and Hardware Decompression Using LZ77, Proceedings of the 2002 IEEE International Test Conference, p.331, October 07-10, 2002
• 28: Hans-Joachim Wunderlich , Gundolf Kiefer, Bit-flipping BIST, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.337-343, November 10-14, 1996, San Jose, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.3 Reliability and Testing**

General Terms:
Algorithms, Design

Keywords:
Embedded core testing, SoC testing, reduced pin-count testing, test application time, test data volume