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The impact of address allocation and routing on the structure and implementation of routing tables
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Source Applications, Technologies, Architectures, and Protocols for Computer Communication archive
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications table of contents
Karlsruhe, Germany
SESSION: Measurement table of contents
Pages: 125 - 136  
Year of Publication: 2003
ISBN:1-58113-735-4
Authors
Harsha Narayan  University of California, San Diego, La Jolla, CA
Ramesh Govindan  University of Southern California, La Jolla, CA
George Varghese  University of California, San Diego, La Jolla, CA
Sponsors
ACM: Association for Computing Machinery
SIGCOMM: ACM Special Interest Group on Data Communication
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 45,   Citation Count: 6
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ABSTRACT

The recent growth in the size of the routing table has led to an interest in quantitatively understanding both the causes (eg multihoming) as well as the effects (eg impact on router lookup implementations) of such routing table growth. In this paper, we describe a new model called ARAM that defines the structure of routing tables of any given size. Unlike simpler empirical models that work backwards from effects (eg current prefix length distributions), ARAM approximately models the causes of table growth (allocation by registries, assignment by ISPs, multihoming and load balancing). We show that ARAM models with high fidelity three abstract measures (prefix distribution, prefix depth, and number of nodes in the tree) of the shape of the prefix tree --- as validated against 20 snapshots of backbone routing tables from 1997 to the present. We then use ARAM for evaluating the scalability of IP lookup schemes, and studying the effects of multihoming and load balancing on their scaling behavior. Our results indicate that algorithmic solutions based on multibit tries will provide more prefixes per chip than TCAMs (as table sizes scale toward a million) unless TCAMs can be engineered to use 8 transistors per cell. By contrast, many of today's SRAM-based TCAMs use 14-16 transistors per cell.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Harsha Narayan: colleagues
Ramesh Govindan: colleagues
George Varghese: colleagues

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