An Upper Bound for 3D Slicing Floorplans

ABSTRACT

As the impact of interconnect on IC performance and chip area in deep submicron design increases, research activities on technologies for three-dimensional integrated circuits intensify. Nevertheless, there is not much work done on the automation of 3D-layout design. In this paper we survey slicing structures for 3D floorplans. We present an upper bound for the volume of such floorplans, which shows the usability of slicing structures for three-dimensional floorplanning.

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