Estimation of Maximum Power-up Current

ABSTRACT

Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-gated circuit must be brought to a valid state from the power-off state, when all nodes in the circuit are at logic zero state, before useful computation can begin. Thus, estimation of the maximum current in a power gated circuit must determine the maximum of all possible power-up and normal switching current. In this paper, we propose a cluster-based ATPG algorithm to estimate the maximum power-up current for combinational circuits. Our method achieves substantial improvement over simulation-based methods and also over the previously proposed ATPG-based methods. Further, we also formulate the sequential circuit maximum current problem as a combinational ATPG problem, and solve it using the cluster-based estimation algorithm. Experimental results show that the maximum power-up current for sequential circuits can be up to 73% larger than the maximum normal switching current.

REFERENCES

• 1: [1] M. Abramovici, M. A. Breuer, and A. D. Friedma. Digital Systems Testing and Testable Design. IEEE PRESS, 1990.
• 2: Jason Cong , Yuzheng Ding, On area/depth trade-off in LUT-based FPGA technology mapping, Proceedings of the 30th international conference on Design automation, p.213-218, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164675]
• 3: Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu, Large scale circuit partitioning with loose/stable net removal and signal flow based clustering, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.441-446, November 09-13, 1997, San Jose, California, United States
• 4: [4] J. T. Kao and A. P. Chandrakasan. Dual-threshold voltage techniques for low-power digital circuits. IEEE Journal of Solid-state circuits, 35(7):1009-1018, July 2000.
• 5: Yong Chang Kim , Kewal K. Saluja , Vishwani D. Agrawal, Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.143, January 03-07, 2001
• 6: Fei Li , Lei He, Maximum current estimation considering power gating, Proceedings of the 2001 international symposium on Physical design, p.106-111, April 01-04, 2001, Sonoma, California, United States [doi>10.1145/369691.369748]
• 7: [7] F. Li, L. He, and K. K. Saluja. Estimation of maximum power-up current. In University of Wisconsin-Madison, Technique Report, ECE-01-2, July 2001.
• 8: [8] F. Li, W. Zhao, and P. Tang. Improved ATPG-based maximum power estimation. Chinese Journal of Computer-Aided Design and Computer Graphics, 12(7):538-543, July 2000.
• 9: [9] S. Thompson, P. Packan, and M. Bohr. MOS scaling: Transistor challenges for the 21st century. Intel Technology Journal, Q3, 1998.
• 10: [10] C.-Y. Wang, K. Roy, and T.-L. Chou. Maximum power estimation for sequential circuits using a test generation based technique. In Proc. IEEE Custom Integrated Circuits Conf., pages 229-232, Apr. 1996.

INDEX TERMS

Keywords:
current estimation, leakage reduction, ATPG algorithm