Evaluating Run-Time Techniques for Leakage Power Reduction

ABSTRACT

While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: Input Vector Control, Body Bias Control and Power Supply Gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving Power Supply Gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings.

REFERENCES

• 1: Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
• 2: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 3: [3] Ferre, A. and Figueras, J., "Characterization of Leakage Power in CMOS Technologies", IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, 1998, pp. 85-188.
• 4: Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280917]
• 5: [5] Johnson, M., Somasekhar, D. and Roy, K., "Models and Algorithms for Bounds in CMOS Circuits", IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 18, No. 6, June 1999, pp. 714-725.
• 6: [6] Ye, Y., Borkar, S., and De, V., "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Symposium on VLSI Circuits, 1998, pp. 40-41.
• 7: S. Bobba , I. N. Hajj, Maximum Leakage Power Estimation for CMOS Circuits, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.116, March 04-05, 1999
• 8: Mark C. Johnson , Dinesh Somasekhar , Kaushik Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, Proceedings of the 36th ACM/IEEE conference on Design automation, p.442-445, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309976]
• 9: [9] Halter J., and Najm, F., "A Gate-level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits", IEEE Custom Integrated Circuits Conference, 1997, pp. 475-478.
• 10: [10] Mutoh, S., Douskei, T., Matsuya, Y., Aoki, T., Shigematsu, S. and Yamada J., "1-V Power Supply High-Speed Digital Circuit Technology with Multi-threshold Voltage CMOS", IEEE Journal of Solid-state Circuits, pp. 847-854, August 1995.
• 11: Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De, Design and optimization of low voltage high performance dual threshold CMOS circuits, Proceedings of the 35th annual conference on Design automation, p.489-494, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277179]
• 12: [12] Kuroda, T., et al, "A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," IEEE Journal of Solid-State Circuits, pp. 1770-1779, November 1996.
• 13: [13] Assaderaghi, F., Sinitsky, D., Parke, S. A., Bokor, J., Ko, P. K. and Hu, C., "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI", IEEE Transactions on Electron Devices, Vol. 44, No. 3, March 1997, pp. 414-422.
• 14: Liqiong Wei , Kaushik Roy , Vivek K. De, Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs, Proceedings of the 13th International Conference on VLSI Design, p.24, January 04-07, 2000
• 15: [15] Dancy, A. and Chandrakasan, A., "Techniques for Aggressive Supply Voltage Scaling and Efficient Regulation", IEEE Custom Integrated Circuits Conference, 1997, pp. 579- 586.
• 16: [16] Jou, S. and Chen, T., "On-Chip Voltage Down Converter for Low Power Digital System", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, No. 5, May 1998, pp. 617-625.
• 17: [17] Von Kaenel, V., et al., "A Voltage Reduction Technique for Battery-Operated Systems", IEEE Journal on Solid-State Circuits, Vol. 25, No. 5, October 1990, pp. 1136-1140.
• 18: [18] Maneatis, J., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques", IEEE Journal on Solid-State Circuits, Vol. 31, No. 11, November 1996, pp. 1723-1732.
• 19: [19] Duarte, D., Vijaykrishnan, N., and Irwin M. J., "A Complete PLL Power Consumption Model", CSE Internal Technical Report, Pennsylvania State University, May 2001.