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High-Level Synthesis with SIMD Units
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2002 Asia and South Pacific Design Automation Conference table of contents
Page: 407  
Year of Publication: 2002
ISBN:0-7695-1441-3
Authors
Vijay Raghunathan  NEC-USA, C&C Research Labs, Princeton, NJ
Mani B. Srivastava
Milos D. Ercegovac
Anand Raghunathan
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
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ABSTRACT

This paper presents novel techniques to integrate the use of Single Instruction Multiple Data (SIMD) functional units in a high-level synthesis (HLS) design methodology. SIMD functional units can be configured to operate in one or more SIMD modes, in which they process multiple sets of smaller bitwidth operands in parallel. Conceptually, the use of SIMD functional units en-ables HLS to (i) exploit parallelism to a higher degree without using additional resources, (ii) improve resource utilization by enabling hardware re-use at a fine-grained level, and (iii) improve energy efficiency for a given area and/or performance constraint.We illustrate the issues involved in performing high-level syn-thesis with SIMD functional units, and discuss how algorithms involved in a typical high-level synthesis flow can be enhanced to result in maximal performance and energy improvements. These techniques are not restricted to specific high-level synthesis tools/algorithms, and can be plugged into any generic high-level synthesis system. Experimental results indicate that, the use of SIMD units can improve performance by up to 1.9X (average of 1.57X), and simultaneously reduce energy consumption by up to 33.16% (average of 28.03%) compared to well-optimized conven-tional designs, with minimal area overheads (average of 2.18%). The performance improvements can be translated into additional energy savings, resulting in upto 66.26% (average of 55.88%) en-ergy reductions. Further, our experiments demonstrate that, the use of SIMD units in a HLS tool results in a shift in the entire area-delay- energy tradeoff envelope that can be obtained, to include de-sirable parts of the design space (i.e., higher quality designs) that were hitherto unreachable.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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[4] "Closing the Gap Between ASIC and Custom: Design Examples", special session #27 at the IEEE/ACM Design Automation Conf., June 2001.
 
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Collaborative Colleagues:
Vijay Raghunathan: colleagues
Mani B. Srivastava: colleagues
Milos D. Ercegovac: colleagues
Anand Raghunathan: colleagues

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